From 72e8cad123284447f7e1c663e9213b7d1e9209ff Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 28 Jul 2025 20:08:32 -0700 Subject: [PATCH] Implement processor_t::paddr_bits correctly It wasn't being called anywhere, so the 50- vs. 56-bit discrepancy never manifested. --- riscv/processor.cc | 7 ------- riscv/processor.h | 2 +- 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index 6fe64abb..47a96c17 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -626,13 +626,6 @@ void processor_t::disasm(insn_t insn) } } -int processor_t::paddr_bits() -{ - unsigned max_xlen = isa.get_max_xlen(); - assert(xlen == max_xlen); - return max_xlen == 64 ? 50 : 34; -} - void processor_t::put_csr(int which, reg_t val) { val = zext_xlen(val); diff --git a/riscv/processor.h b/riscv/processor.h index a6e9eeb1..ff4be9e9 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -273,6 +273,7 @@ public: mmu_t* get_mmu() { return mmu; } state_t* get_state() { return &state; } unsigned get_xlen() const { return xlen; } + unsigned paddr_bits() { return isa.get_max_xlen() == 64 ? 56 : 34; } unsigned get_const_xlen() const { // Any code that assumes a const xlen should use this method to // document that assumption. If Spike ever changes to allow @@ -422,7 +423,6 @@ private: void take_trigger_action(triggers::action_t action, reg_t breakpoint_tval, reg_t epc, bool virt); void disasm(insn_t insn); // disassemble and print an instruction void register_insn(insn_desc_t, bool); - int paddr_bits(); void enter_debug_mode(uint8_t cause, uint8_t ext_cause);