Convert sentropy to csr_t

riscv/csrs.cc

@@ -1156,3 +1156,24 @@ bool composite_csr_t::unlogged_write(const reg_t val) noexcept {
   lower_csr->write(val);
   return false;  // logging is done only by the underlying CSRs
 }
+
+
+sentropy_csr_t::sentropy_csr_t(processor_t* const proc, const reg_t addr):
+  csr_t(proc, addr) {
+}
+
+void sentropy_csr_t::verify_permissions(insn_t insn, bool write) const {
+  /* Read-only access disallowed due to wipe-on-read side effect */
+  if (!proc->extension_enabled(EXT_ZKR) || !write)
+    throw trap_illegal_instruction(insn.bits());
+  csr_t::verify_permissions(insn, write);
+}
+
+reg_t sentropy_csr_t::read() const noexcept {
+  return proc->es.get_sentropy();
+}
+
+bool sentropy_csr_t::unlogged_write(const reg_t val) noexcept {
+  proc->es.set_sentropy(val);
+  return true;
+}

riscv/csrs.h

@@ -603,4 +603,15 @@ class composite_csr_t: public csr_t {
   const unsigned upper_lsb;
 };
 
+
+class sentropy_csr_t: public csr_t {
+ public:
+  sentropy_csr_t(processor_t* const proc, const reg_t addr);
+  virtual void verify_permissions(insn_t insn, bool write) const override;
+  virtual reg_t read() const noexcept override;
+ protected:
+  virtual bool unlogged_write(const reg_t val) noexcept override;
+};
+
+
 #endif

riscv/processor.cc

@@ -525,6 +525,9 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   csrmap[CSR_FRM] = frm = std::make_shared<float_csr_t>(proc, CSR_FRM, FSR_RD >> FSR_RD_SHIFT, 0);
   assert(FSR_AEXC_SHIFT == 0);  // composite_csr_t assumes fflags begins at bit 0
   csrmap[CSR_FCSR] = std::make_shared<composite_csr_t>(proc, CSR_FFLAGS, frm, fflags, FSR_RD_SHIFT);
+
+  csrmap[CSR_SENTROPY] = std::make_shared<sentropy_csr_t>(proc, CSR_SENTROPY);
+
   serialized = false;
 
 #ifdef RISCV_ENABLE_COMMITLOG
@@ -976,9 +979,6 @@ void processor_t::set_csr(int which, reg_t val)
 
   switch (which)
   {
-    case CSR_SENTROPY:
-      es.set_sentropy(val);
-      break;
     case CSR_VCSR:
       dirty_vs_state;
       VU.vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
@@ -1015,10 +1015,6 @@ void processor_t::set_csr(int which, reg_t val)
     case CSR_VXRM:
       LOG_CSR(CSR_VXRM);
       break;
-
-    case CSR_SENTROPY:
-      LOG_CSR(which);
-      break;
   }
 #endif
 }
@@ -1043,13 +1039,6 @@ reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek)
 
   switch (which)
   {
-    case CSR_SENTROPY:
-      if (!extension_enabled(EXT_ZKR))
-        break;
-      /* Read-only access disallowed due to wipe-on-read side effect */
-      if (!write && !peek)
-        break;
-      ret(es.get_sentropy());
     case CSR_VCSR:
       require_vector_vs;
       if (!extension_enabled('V'))

riscv/processor.h

@@ -468,8 +468,6 @@ private:
   std::vector<bool> extension_table;
   std::vector<bool> impl_table;
 
-  entropy_source es; // Crypto ISE Entropy source.
-
   std::vector<insn_desc_t> instructions;
   std::map<reg_t,uint64_t> pc_histogram;
 
@@ -500,6 +498,8 @@ private:
   // Track repeated executions for processor_t::disasm()
   uint64_t last_pc, last_bits, executions;
 public:
+  entropy_source es; // Crypto ISE Entropy source.
+
   reg_t n_pmp;
   reg_t lg_pmp_granularity;
   reg_t pmp_tor_mask() { return -(reg_t(1) << (lg_pmp_granularity - PMP_SHIFT)); }