[sim, xcc] added PCRs to replace k0 and k1

riscv/insns/mfpcr.h

@@ -25,6 +25,13 @@ switch(insn.rtype.rb)
     val = sim->get_fromhost();
     break;
 
+  case 24:
+    val = pcr_k0;
+    break;
+  case 25:
+    val = pcr_k1;
+    break;
+
   default:
     val = -1;
 }

riscv/insns/mtpcr.h

@@ -17,4 +17,11 @@ switch(insn.rtype.rb)
   case 16:
     sim->set_tohost(val);
     break;
+
+  case 24:
+    pcr_k0 = val;
+    break;
+  case 25:
+    pcr_k1 = val;
+    break;
 }

riscv/insns/mwfpcr.h

@@ -1,28 +0,0 @@
-require_supervisor;
-
-switch(insn.rtype.rb)
-{
-  case 0:
-    RA = sext32(sr);
-    break;
-  case 1:
-    RA = sext32(epc);
-    break;
-  case 2:
-    RA = sext32(badvaddr);
-    break;
-  case 3:
-    RA = sext32(ebase);
-    break;
-
-  case 8:
-    RA = sext32(MEMSIZE >> 12);
-    break;
-
-  case 17:
-    RA = sext32(sim->get_fromhost());
-    break;
-
-  default:
-    RA = -1;
-}

riscv/insns/mwtpcr.h

@@ -1,18 +0,0 @@
-require_supervisor;
-
-switch(insn.rtype.rb)
-{
-  case 0:
-    set_sr(sext32(RA));
-    break;
-  case 1:
-    epc = sext32(RA);
-    break;
-  case 3:
-    ebase = sext32(RA & ~0xFFF);
-    break;
-
-  case 16:
-    sim->set_tohost(sext32(RA));
-    break;
-}

riscv/insns/slori.h

@@ -1 +0,0 @@
-RA = (RA << 32) | (BIGIMM << IMM_BITS);

riscv/processor.h

@@ -27,6 +27,8 @@ private:
   reg_t epc;
   reg_t badvaddr;
   reg_t ebase;
+  reg_t pcr_k0;
+  reg_t pcr_k1;
   uint32_t id;
   uint32_t sr;