diff --git a/riscv/processor.cc b/riscv/processor.cc
index 9cfd4ad5..76a54172 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -397,7 +397,7 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT
 
     vill = !(vflmul >= 0.125 && vflmul <= 8)
            || vsew > ELEN
-           || vflmul < ((float)vsew / ELEN)
+           || vflmul < ((float)vsew_min / ELEN)
            || vediv != 1
            || (newType >> 8) != 0;
 
diff --git a/riscv/processor.h b/riscv/processor.h
index 74ad526d..3e6b3e94 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -488,6 +488,7 @@ public:
       reg_t vstart, vxrm, vxsat, vl, vtype, vlenb;
       reg_t vma, vta;
       reg_t vediv, vsew;
+      const reg_t vsew_min = 8; // the narrowest supported SEW value at LMUL=1
       float vflmul;
       reg_t ELEN, VLEN;
       bool vill;