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@ -78,11 +78,11 @@ public: |
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store_func(uint64) |
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store_func(uint64) |
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// load instruction from memory at aligned address.
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// load instruction from memory at aligned address.
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inline icache_entry_t access_icache(reg_t addr) |
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inline icache_entry_t* access_icache(reg_t addr) |
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{ |
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{ |
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reg_t idx = (addr / sizeof(insn_t)) % ICACHE_SIZE; |
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reg_t idx = (addr / sizeof(insn_t)) % ICACHE_SIZE; |
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icache_entry_t entry = icache[idx]; |
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icache_entry_t* entry = &icache[idx]; |
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if (likely(entry.tag == addr)) |
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if (likely(entry->tag == addr)) |
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return entry; |
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return entry; |
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void* iaddr = translate(addr, sizeof(insn_t), false, true); |
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void* iaddr = translate(addr, sizeof(insn_t), false, true); |
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@ -99,12 +99,12 @@ public: |
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icache[idx].tag = -1; |
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icache[idx].tag = -1; |
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tracer.trace(paddr, sizeof(insn_t), false, true); |
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tracer.trace(paddr, sizeof(insn_t), false, true); |
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} |
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} |
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return icache[idx]; |
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return &icache[idx]; |
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} |
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} |
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inline insn_fetch_t load_insn(reg_t addr) |
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inline insn_fetch_t load_insn(reg_t addr) |
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{ |
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{ |
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return access_icache(addr).data; |
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return access_icache(addr)->data; |
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} |
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} |
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void set_processor(processor_t* p) { proc = p; flush_tlb(); } |
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void set_processor(processor_t* p) { proc = p; flush_tlb(); } |
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