vxcptsave->vxcptevac,vxcptrestore->vxcpthold

this change was necessary since the impl csr is gone.

hwacha/decode_hwacha.h

@@ -14,6 +14,7 @@
 #define MAXVL (h->get_ct_state()->maxvl)
 #define VL (h->get_ct_state()->vl)
 #define UTIDX (h->get_ct_state()->count)
+#define PREC (h->get_ct_state()->prec)
 #define VF_PC (h->get_ct_state()->vf_pc)
 #define WRITE_NXPR(nxprnext) (h->get_ct_state()->nxpr = (nxprnext))
 #define WRITE_NFPR(nfprnext) (h->get_ct_state()->nfpr = (nfprnext))

hwacha/encodings_hwacha.h

@@ -111,7 +111,7 @@
 #define MASK_VXCPTAUX  0xfffff07f
 #define MASK_VXCPTCAUSE  0xfffff07f
 #define MASK_VXCPTEVAC  0xfff07fff
-#define MASK_VXCPTHOLD  0xffffffff
+#define MASK_VXCPTHOLD  0xfff07fff
 #define MASK_VXCPTKILL  0xffffffff
 #define MASK_VXCPTRESTORE  0xfff07fff
 #define MASK_VXCPTSAVE  0xfff07fff

hwacha/hwacha_disasm.cc

@@ -139,8 +139,8 @@ std::vector<disasm_insn_t*> hwacha_t::get_disasms()
 
   DISASM_INSN("vxcptcause", vxcptcause, 0, {&xrd});
   DISASM_INSN("vxcptaux", vxcptaux, 0, {&xrd});
-  DISASM_INSN("vxcptsave", vxcptsave, 0, {&xrs1});
+  DISASM_INSN("vxcptevac", vxcptevac, 0, {&xrs1});
-  DISASM_INSN("vxcptrestore", vxcptrestore, 0, {&xrs1});
+  DISASM_INSN("vxcpthold", vxcpthold, 0, {&xrs1});
   DISASM_INSN("vxcptkill", vxcptkill, 0, {});
 
   const uint32_t mask_vseglen = 0x7UL << 29;

hwacha/insns/vxcptsave.h → hwacha/insns/vxcptevac.h

@@ -13,12 +13,16 @@ reg_t addr = XS1;
   p->get_mmu()->store_uint64(addr, value); \
   addr += 8; \
 
+// to be compliant with the evac structure
+STORE_D(addr, (uint64_t)-1);
+
 STORE_W(addr, NXPR);
 STORE_W(addr, NFPR);
 STORE_W(addr, MAXVL);
 STORE_W(addr, VL);
 STORE_W(addr, UTIDX);
-addr += 4;
+STORE_W(addr, PREC);
+
 STORE_D(addr, VF_PC);
 
 for (uint32_t x=1; x<NXPR; x++) {

hwacha/insns/vxcptrestore.h → hwacha/insns/vxcpthold.h

@@ -10,13 +10,15 @@ reg_t addr = XS1;
 #define LOAD_D(addr) \
   (addr += 8, p->get_mmu()->load_uint64(addr-8))
 
+// to be compliant with the evac structure
+addr += 8;
 
 WRITE_NXPR(LOAD_W(addr));
 WRITE_NFPR(LOAD_W(addr));
 WRITE_MAXVL(LOAD_W(addr));
 WRITE_VL(LOAD_W(addr));
 WRITE_UTIDX(LOAD_W(addr));
-addr += 4;
+WRITE_PREC(LOAD_W(addr));
 WRITE_VF_PC(LOAD_D(addr));
 
 for (uint32_t x=1; x<NXPR; x++) {

hwacha/opcodes_hwacha.h

@@ -42,6 +42,6 @@ DECLARE_INSN(vssegstw, MATCH_VSSEGSTW, MASK_VSSEGSTW)
 DECLARE_INSN(vssegw, MATCH_VSSEGW, MASK_VSSEGW)
 DECLARE_INSN(vxcptaux, MATCH_VXCPTAUX, MASK_VXCPTAUX)
 DECLARE_INSN(vxcptcause, MATCH_VXCPTCAUSE, MASK_VXCPTCAUSE)
+DECLARE_INSN(vxcptevac, MATCH_VXCPTEVAC, MASK_VXCPTEVAC)
+DECLARE_INSN(vxcpthold, MATCH_VXCPTHOLD, MASK_VXCPTHOLD)
 DECLARE_INSN(vxcptkill, MATCH_VXCPTKILL, MASK_VXCPTKILL)
-DECLARE_INSN(vxcptrestore, MATCH_VXCPTRESTORE, MASK_VXCPTRESTORE)
-DECLARE_INSN(vxcptsave, MATCH_VXCPTSAVE, MASK_VXCPTSAVE)