diff --git a/riscv/insns/vfmv_v_f.h b/riscv/insns/vfmv_v_f.h
index 9f66004d..50b7513c 100644
--- a/riscv/insns/vfmv_v_f.h
+++ b/riscv/insns/vfmv_v_f.h
@@ -1,31 +1,4 @@
 // vfmv_vf vd, vs1
-require_align(insn.rd(), P.VU.vflmul);
-VI_VFP_COMMON
-switch(P.VU.vsew) {
-  case e16:
-    for (reg_t i=P.VU.vstart->read(); i<vl; ++i) {
-      auto &vd = P.VU.elt<float16_t>(rd_num, i, true);
-      auto rs1 = f16(READ_FREG(rs1_num));
-
-      vd = rs1;
-    }
-    break;
-  case e32:
-    for (reg_t i=P.VU.vstart->read(); i<vl; ++i) {
-      auto &vd = P.VU.elt<float32_t>(rd_num, i, true);
-      auto rs1 = f32(READ_FREG(rs1_num));
-
-      vd = rs1;
-    }
-    break;
-  case e64:
-    for (reg_t i=P.VU.vstart->read(); i<vl; ++i) {
-      auto &vd = P.VU.elt<float64_t>(rd_num, i, true);
-      auto rs1 = f64(READ_FREG(rs1_num));
-
-      vd = rs1;
-    }
-    break;
-}
-
-P.VU.vstart->write(0);
+VI_VF_MERGE_LOOP({
+  vd = rs1;
+})