Zbkx renames xperm.n and xperm.b as xperm4 and xperm8. (#846)

Krypto 1.0 changes: Entropy source CSR, name.
List scalar crypto instruction groupings, as there is no single K extension.

Co-authored-by: Markku-Juhani O. Saarinen <mjos@mjos.fi>

README.md

@@ -18,7 +18,8 @@ Spike supports the following RISC-V ISA features:
   - D extension, v2.2
   - Q extension, v2.2
   - C extension, v2.0
-  - K extension, v0.8.1 ([Scalar Cryptography](https://github.com/riscv/riscv-crypto))
+  - Zbkb, Zbkc, Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh scalar cryptography extensions (Zk, Zkn, and Zks groups), v1.0
+  - Zkr virtual entropy source emulation, v1.0
   - V extension, v1.0 (_requires a 64-bit host_)
   - P extension, v0.9.2
   - Zba extension, v1.0

disasm/disasm.cc

@@ -836,16 +836,16 @@ disassembler_t::disassembler_t(int xlen)
   DEFINE_RTYPE(grev);
   add_insn(new disasm_insn_t("rev", match_grevi | ((xlen - 1) << imm_shift), mask_grevi | mask_imm, {&xrd, &xrs1}));
   add_insn(new disasm_insn_t("rev8", match_grevi | ((xlen - 8) << imm_shift), mask_grevi | mask_imm, {&xrd, &xrs1}));
-  add_insn(new disasm_insn_t("rev.b", match_grevi | (0x7 << imm_shift), mask_grevi | mask_imm, {&xrd, &xrs1})); // brev8
+  add_insn(new disasm_insn_t("brev8", match_grevi | (0x7 << imm_shift), mask_grevi | mask_imm, {&xrd, &xrs1})); // brev8
   add_insn(new disasm_insn_t("rev8.h", match_grevi | (0x8 << imm_shift), mask_grevi | mask_imm, {&xrd, &xrs1})); // swap16
   DEFINE_ITYPE_SHIFT(grevi);
   DEFINE_RTYPE(gorc);
   add_insn(new disasm_insn_t("orc.b", match_gorci | (0x7 << imm_shift), mask_grevi | mask_imm, {&xrd, &xrs1}));
   DEFINE_ITYPE_SHIFT(gorci);
-  DEFINE_RTYPE(xperm_n);
-  DEFINE_RTYPE(xperm_b);
-  DEFINE_RTYPE(xperm_h);
-  DEFINE_RTYPE(xperm_w);
+  DEFINE_RTYPE(xperm4);
+  DEFINE_RTYPE(xperm8);
+  DEFINE_RTYPE(xperm16);
+  DEFINE_RTYPE(xperm32);
 
   DEFINE_R3TYPE(cmix);
   DEFINE_R3TYPE(fsr);

riscv/csrs.cc

@@ -1181,23 +1181,24 @@ bool composite_csr_t::unlogged_write(const reg_t val) noexcept {
 }
 
 
-sentropy_csr_t::sentropy_csr_t(processor_t* const proc, const reg_t addr):
+seed_csr_t::seed_csr_t(processor_t* const proc, const reg_t addr):
   csr_t(proc, addr) {
 }
 
-void sentropy_csr_t::verify_permissions(insn_t insn, bool write) const {
+void seed_csr_t::verify_permissions(insn_t insn, bool write) const {
   /* Read-only access disallowed due to wipe-on-read side effect */
+  /* XXX mseccfg.sseed and mseccfg.useed should be verified. */
   if (!proc->extension_enabled(EXT_ZKR) || !write)
     throw trap_illegal_instruction(insn.bits());
   csr_t::verify_permissions(insn, write);
 }
 
-reg_t sentropy_csr_t::read() const noexcept {
-  return proc->es.get_sentropy();
+reg_t seed_csr_t::read() const noexcept {
+  return proc->es.get_seed();
 }
 
-bool sentropy_csr_t::unlogged_write(const reg_t val) noexcept {
-  proc->es.set_sentropy(val);
+bool seed_csr_t::unlogged_write(const reg_t val) noexcept {
+  proc->es.set_seed(val);
   return true;
 }
 

riscv/csrs.h

@@ -611,9 +611,9 @@ class composite_csr_t: public csr_t {
 };
 
 
-class sentropy_csr_t: public csr_t {
+class seed_csr_t: public csr_t {
  public:
-  sentropy_csr_t(processor_t* const proc, const reg_t addr);
+  seed_csr_t(processor_t* const proc, const reg_t addr);
   virtual void verify_permissions(insn_t insn, bool write) const override;
   virtual reg_t read() const noexcept override;
  protected:

riscv/encoding.h

@@ -1,6 +1,6 @@
 /*
  * This file is auto-generated by running 'make ../riscv-isa-sim/riscv/encoding.h' in
- * https://github.com/riscv/riscv-opcodes (70c120b)
+ * https://github.com/riscv/riscv-opcodes (ce0bd39)
  */
 
 /* See LICENSE for license details. */
@@ -833,12 +833,12 @@
 #define MASK_SHFLI  0xfe00707f
 #define MATCH_UNSHFLI 0x8005013
 #define MASK_UNSHFLI  0xfe00707f
-#define MATCH_XPERM_N 0x28002033
-#define MASK_XPERM_N  0xfe00707f
-#define MATCH_XPERM_B 0x28004033
-#define MASK_XPERM_B  0xfe00707f
-#define MATCH_XPERM_H 0x28006033
-#define MASK_XPERM_H  0xfe00707f
+#define MATCH_XPERM4 0x28002033
+#define MASK_XPERM4  0xfe00707f
+#define MATCH_XPERM8 0x28004033
+#define MASK_XPERM8  0xfe00707f
+#define MATCH_XPERM16 0x28006033
+#define MASK_XPERM16  0xfe00707f
 #define MATCH_BMATFLIP 0x60301013
 #define MASK_BMATFLIP  0xfff0707f
 #define MATCH_CRC32_D 0x61301013
@@ -921,8 +921,8 @@
 #define MASK_PACKUW  0xfe00707f
 #define MATCH_BFPW 0x4800703b
 #define MASK_BFPW  0xfe00707f
-#define MATCH_XPERM_W 0x28000033
-#define MASK_XPERM_W  0xfe00707f
+#define MATCH_XPERM32 0x28000033
+#define MASK_XPERM32  0xfe00707f
 #define MATCH_ECALL 0x73
 #define MASK_ECALL  0xffffffff
 #define MATCH_EBREAK 0x100073
@@ -2800,6 +2800,7 @@
 #define CSR_VXSAT 0x9
 #define CSR_VXRM 0xa
 #define CSR_VCSR 0xf
+#define CSR_SEED 0x15
 #define CSR_CYCLE 0xc00
 #define CSR_TIME 0xc01
 #define CSR_INSTRET 0xc02
@@ -2995,7 +2996,6 @@
 #define CSR_MARCHID 0xf12
 #define CSR_MIMPID 0xf13
 #define CSR_MHARTID 0xf14
-#define CSR_SENTROPY 0x546
 #define CSR_HTIMEDELTAH 0x615
 #define CSR_CYCLEH 0xc80
 #define CSR_TIMEH 0xc81
@@ -3358,9 +3358,9 @@ DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH)
 DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP)
 DECLARE_INSN(shfli, MATCH_SHFLI, MASK_SHFLI)
 DECLARE_INSN(unshfli, MATCH_UNSHFLI, MASK_UNSHFLI)
-DECLARE_INSN(xperm_n, MATCH_XPERM_N, MASK_XPERM_N)
-DECLARE_INSN(xperm_b, MATCH_XPERM_B, MASK_XPERM_B)
-DECLARE_INSN(xperm_h, MATCH_XPERM_H, MASK_XPERM_H)
+DECLARE_INSN(xperm4, MATCH_XPERM4, MASK_XPERM4)
+DECLARE_INSN(xperm8, MATCH_XPERM8, MASK_XPERM8)
+DECLARE_INSN(xperm16, MATCH_XPERM16, MASK_XPERM16)
 DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP)
 DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D)
 DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D)
@@ -3402,7 +3402,7 @@ DECLARE_INSN(bdecompressw, MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW)
 DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
 DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW)
 DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW)
-DECLARE_INSN(xperm_w, MATCH_XPERM_W, MASK_XPERM_W)
+DECLARE_INSN(xperm32, MATCH_XPERM32, MASK_XPERM32)
 DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
 DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
 DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
@@ -4347,6 +4347,7 @@ DECLARE_CSR(vstart, CSR_VSTART)
 DECLARE_CSR(vxsat, CSR_VXSAT)
 DECLARE_CSR(vxrm, CSR_VXRM)
 DECLARE_CSR(vcsr, CSR_VCSR)
+DECLARE_CSR(seed, CSR_SEED)
 DECLARE_CSR(cycle, CSR_CYCLE)
 DECLARE_CSR(time, CSR_TIME)
 DECLARE_CSR(instret, CSR_INSTRET)
@@ -4542,7 +4543,6 @@ DECLARE_CSR(mvendorid, CSR_MVENDORID)
 DECLARE_CSR(marchid, CSR_MARCHID)
 DECLARE_CSR(mimpid, CSR_MIMPID)
 DECLARE_CSR(mhartid, CSR_MHARTID)
-DECLARE_CSR(sentropy, CSR_SENTROPY)
 DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH)
 DECLARE_CSR(cycleh, CSR_CYCLEH)
 DECLARE_CSR(timeh, CSR_TIMEH)

riscv/entropy_source.h

@@ -11,7 +11,7 @@ class entropy_source {
 
 public:
 
-  // Valid return codes for OPST bits [31:30] when reading sentropy.
+  // Valid return codes for OPST bits [31:30] when reading seed.
   static const uint32_t OPST_BIST = 0x0 << 30;
   static const uint32_t OPST_WAIT = 0x1 << 30;
   static const uint32_t OPST_ES16 = 0x2 << 30;
@@ -27,20 +27,20 @@ public:
   }
 
   //
-  // sentropy register
+  // seed register
   // ------------------------------------------------------------
 
-  void set_sentropy(reg_t val) {
-    // Always ignore writes to sentropy.
+  void set_seed(reg_t val) {
+    // Always ignore writes to seed.
     // This CSR is strictly read only. It occupies a RW CSR address
     // to handle the side-effect of the changing seed value on a read.
   }
 
 
   //
-  // The format of sentropy is described in Section 4.1 of
+  // The format of seed is described in Section 4.1 of
   // the scalar cryptography specification.
-  reg_t get_sentropy() {
+  reg_t get_seed() {
 
     uint32_t result  = 0;
 
@@ -53,8 +53,8 @@ public:
     if(return_status == OPST_ES16) {
 
         // Add some sampled entropy into the low 16 bits
-        uint16_t seed  = this -> get_two_random_bytes();
-        result        |= seed;
+        uint16_t entropy = this -> get_two_random_bytes();
+        result |= entropy;
 
     } else if(return_status == OPST_BIST) {
 

riscv/processor.cc

@@ -526,7 +526,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   assert(FSR_AEXC_SHIFT == 0);  // composite_csr_t assumes fflags begins at bit 0
   csrmap[CSR_FCSR] = std::make_shared<composite_csr_t>(proc, CSR_FCSR, frm, fflags, FSR_RD_SHIFT);
 
-  csrmap[CSR_SENTROPY] = std::make_shared<sentropy_csr_t>(proc, CSR_SENTROPY);
+  csrmap[CSR_SEED] = std::make_shared<seed_csr_t>(proc, CSR_SEED);
 
   csrmap[CSR_MARCHID] = std::make_shared<const_csr_t>(proc, CSR_MARCHID, 5);
   csrmap[CSR_MIMPID] = std::make_shared<const_csr_t>(proc, CSR_MIMPID, 0);

riscv/riscv.mk.in

@@ -426,10 +426,10 @@ riscv_insn_ext_b = \
 	unshfli \
 	unshflw \
 	xnor \
-	xperm_n \
-	xperm_b \
-	xperm_h \
-	xperm_w \
+	xperm4 \
+	xperm8 \
+	xperm16 \
+	xperm32 \
 
 # Scalar Crypto ISE
 riscv_insn_ext_k = \