From 60743fe5c582dfe79d28493bcd1ddc34f76b0416 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sat, 30 Mar 2019 15:09:15 -0700 Subject: [PATCH] RV32Q is not invalid https://github.com/riscv/riscv-isa-manual/commit/013ba6dc8a504ee4ad7bee42554fecaef7ba797f#diff-2a8fece1cbcdf623cafbce866ea7d4d0R7 --- riscv/processor.cc | 3 --- 1 file changed, 3 deletions(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index f8c44466..189b7db5 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -113,9 +113,6 @@ void processor_t::parse_isa_string(const char* str) if (supports_extension('Q') && !supports_extension('D')) bad_isa_string(str); - if (supports_extension('Q') && max_xlen < 64) - bad_isa_string(str); - max_isa = state.misa; }