[pk,sim,xcc] Renamed instructions to RISC-V spec

All word-sized arithmetic operations are now postfixed with 'w',
and all double-word-sized arithmetic operations are no longer
prefixed with 'd'.  mtc0/mfc0 are removed and replaced with
mfpcr/mtpcr/mwfpcr/mwtpcr.

riscv/execute.h

@@ -585,7 +585,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x1:
       {
-        #include "insns/daddi.h"
+        #include "insns/addiw.h"
         break;
       }
       case 0x2:
@@ -714,14 +714,14 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/srlv.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea004020)
+        if((insn.bits & 0xfe007fe0) == 0xea004060)
         {
-          #include "insns/sllv.h"
+          #include "insns/srav.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea004060)
+        if((insn.bits & 0xfe007fe0) == 0xea004020)
         {
-          #include "insns/srav.h"
+          #include "insns/sllv.h"
           break;
         }
         #include "insns/unimp.h"
@@ -766,14 +766,14 @@ switch((insn.bits >> 0x19) & 0x7f)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe007fe0) == 0xec000020)
+        if((insn.bits & 0xfe007fe0) == 0xec000000)
         {
-          #include "insns/dsub.h"
+          #include "insns/addw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xec000000)
+        if((insn.bits & 0xfe007fe0) == 0xec000020)
         {
-          #include "insns/dadd.h"
+          #include "insns/subw.h"
           break;
         }
         #include "insns/unimp.h"
@@ -782,56 +782,56 @@ switch((insn.bits >> 0x19) & 0x7f)
       {
         if((insn.bits & 0xfe007fe0) == 0xec0010e0)
         {
-          #include "insns/dremu.h"
+          #include "insns/remuw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xec001080)
+        if((insn.bits & 0xfe007fe0) == 0xec0010a0)
         {
-          #include "insns/ddiv.h"
+          #include "insns/divuw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xec0010c0)
+        if((insn.bits & 0xfe007fe0) == 0xec001060)
         {
-          #include "insns/drem.h"
+          #include "insns/mulhuw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xec001060)
+        if((insn.bits & 0xfe007fe0) == 0xec001000)
         {
-          #include "insns/dmulhu.h"
+          #include "insns/mulw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xec001000)
+        if((insn.bits & 0xfe007fe0) == 0xec0010c0)
         {
-          #include "insns/dmul.h"
+          #include "insns/remw.h"
           break;
         }
         if((insn.bits & 0xfe007fe0) == 0xec001040)
         {
-          #include "insns/dmulh.h"
+          #include "insns/mulhw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xec0010a0)
+        if((insn.bits & 0xfe007fe0) == 0xec001080)
         {
-          #include "insns/ddivu.h"
+          #include "insns/divw.h"
           break;
         }
         #include "insns/unimp.h"
       }
       case 0x4:
       {
-        if((insn.bits & 0xfe007fe0) == 0xec004020)
+        if((insn.bits & 0xfe007fe0) == 0xec004060)
         {
-          #include "insns/dsllv.h"
+          #include "insns/sravw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xec004060)
+        if((insn.bits & 0xfe007fe0) == 0xec004020)
         {
-          #include "insns/dsrav.h"
+          #include "insns/sllvw.h"
           break;
         }
         if((insn.bits & 0xfe007fe0) == 0xec004040)
         {
-          #include "insns/dsrlv.h"
+          #include "insns/srlvw.h"
           break;
         }
         #include "insns/unimp.h"
@@ -840,26 +840,26 @@ switch((insn.bits >> 0x19) & 0x7f)
       {
         if((insn.bits & 0xfff07c00) == 0xec005000)
         {
-          #include "insns/dsll.h"
+          #include "insns/sllw.h"
           break;
         }
         if((insn.bits & 0xfff07c00) == 0xec005400)
         {
-          #include "insns/dsll32.h"
+          #include "insns/sll32.h"
           break;
         }
         #include "insns/unimp.h"
       }
       case 0x6:
       {
-        if((insn.bits & 0xfff07c00) == 0xec006400)
+        if((insn.bits & 0xfff07c00) == 0xec006000)
         {
-          #include "insns/dsrl32.h"
+          #include "insns/srlw.h"
           break;
         }
-        if((insn.bits & 0xfff07c00) == 0xec006000)
+        if((insn.bits & 0xfff07c00) == 0xec006400)
         {
-          #include "insns/dsrl.h"
+          #include "insns/srl32.h"
           break;
         }
         #include "insns/unimp.h"
@@ -868,12 +868,12 @@ switch((insn.bits >> 0x19) & 0x7f)
       {
         if((insn.bits & 0xfff07c00) == 0xec007400)
         {
-          #include "insns/dsra32.h"
+          #include "insns/sra32.h"
           break;
         }
         if((insn.bits & 0xfff07c00) == 0xec007000)
         {
-          #include "insns/dsra.h"
+          #include "insns/sraw.h"
           break;
         }
         #include "insns/unimp.h"
@@ -1101,7 +1101,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       {
         if((insn.bits & 0xfe007fff) == 0xfc004000)
         {
-          #include "insns/mfc0.h"
+          #include "insns/mfpcr.h"
           break;
         }
         #include "insns/unimp.h"
@@ -1110,7 +1110,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       {
         if((insn.bits & 0xfe007fff) == 0xfc005000)
         {
-          #include "insns/dmfc0.h"
+          #include "insns/mwfpcr.h"
           break;
         }
         #include "insns/unimp.h"
@@ -1119,7 +1119,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       {
         if((insn.bits & 0xfe007fff) == 0xfc006000)
         {
-          #include "insns/mtc0.h"
+          #include "insns/mtpcr.h"
           break;
         }
         #include "insns/unimp.h"
@@ -1128,7 +1128,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       {
         if((insn.bits & 0xfe007fff) == 0xfc007000)
         {
-          #include "insns/dmtc0.h"
+          #include "insns/mwtpcr.h"
           break;
         }
         #include "insns/unimp.h"

riscv/insns/add.h

@@ -1,2 +1,2 @@
-RC = sext32(RA + RB);
-
+require64;
+RC = RA + RB;

riscv/insns/addi.h

@@ -1 +1,2 @@
-RA = sext32(SIMM + RB);
+require64;
+RA = SIMM + RB;

riscv/insns/addiw.h

@@ -0,0 +1 @@
+RA = sext32(SIMM + RB);

riscv/insns/addw.h

@@ -0,0 +1,2 @@
+RC = sext32(RA + RB);
+

riscv/insns/dadd.h

@@ -1,2 +0,0 @@
-require64;
-RC = RA + RB;

riscv/insns/daddi.h

@@ -1,2 +0,0 @@
-require64;
-RA = SIMM + RB;

riscv/insns/ddiv.h

@@ -1,2 +0,0 @@
-require64;
-RC = sreg_t(RA) / sreg_t(RB);

riscv/insns/ddivu.h

@@ -1,2 +0,0 @@
-require64;
-RC = RA / RB;

riscv/insns/div.h

@@ -1,2 +1,2 @@
-RC = sext32(int32_t(RA)/int32_t(RB));
-
+require64;
+RC = sreg_t(RA) / sreg_t(RB);

riscv/insns/divu.h

@@ -1,2 +1,2 @@
-RC = sext32(uint32_t(RA)/uint32_t(RB));
-
+require64;
+RC = RA / RB;

riscv/insns/divuw.h

@@ -0,0 +1,2 @@
+RC = sext32(uint32_t(RA)/uint32_t(RB));
+

riscv/insns/divw.h

@@ -0,0 +1,2 @@
+RC = sext32(int32_t(RA)/int32_t(RB));
+

riscv/insns/dmul.h

@@ -1,2 +0,0 @@
-require64;
-RC = RA * RB;

riscv/insns/dmulh.h

@@ -1,4 +0,0 @@
-require64;
-int64_t rb = RA;
-int64_t ra = RB;
-RC = (int128_t(rb) * int128_t(ra)) >> 64;

riscv/insns/dmulhu.h

@@ -1,2 +0,0 @@
-require64;
-RC = (uint128_t(RA) * uint128_t(RB)) >> 64;

riscv/insns/drem.h

@@ -1,2 +0,0 @@
-require64;
-RC = sreg_t(RA) % sreg_t(RB);

riscv/insns/dremu.h

@@ -1,2 +0,0 @@
-require64;
-RC = RA % RB;

riscv/insns/dsll.h

@@ -1,2 +0,0 @@
-require64;
-RC = RB << SHAMT;

riscv/insns/dsllv.h

@@ -1,2 +0,0 @@
-require64;
-RC = RB << (RA & 0x3F);

riscv/insns/dsra.h

@@ -1,2 +0,0 @@
-require64;
-RC = sreg_t(RB) >> SHAMT;

riscv/insns/dsrav.h

@@ -1,2 +0,0 @@
-require64;
-RC = RB >> (RA & 0x3F);

riscv/insns/dsrl.h

@@ -1,2 +0,0 @@
-require64;
-RC = RB >> SHAMT;

riscv/insns/dsrlv.h

@@ -1,2 +0,0 @@
-require64;
-RC = RB >> (RA & 0x3F);

riscv/insns/dsub.h

@@ -1,2 +0,0 @@
-require64;
-RC = RA - RB;

riscv/insns/mul.h

@@ -1,2 +1,2 @@
-RC = sext32(RA * RB);
-
+require64;
+RC = RA * RB;

riscv/insns/mulh.h

@@ -1,2 +1,4 @@
-RC = sext32((sreg_t(RA) * sreg_t(RB)) >> 32);
-
+require64;
+int64_t rb = RA;
+int64_t ra = RB;
+RC = (int128_t(rb) * int128_t(ra)) >> 64;

riscv/insns/mulhu.h

@@ -1,2 +1,2 @@
-RC = sext32((RA * RB) >> 32);
-
+require64;
+RC = (uint128_t(RA) * uint128_t(RB)) >> 64;

riscv/insns/mulhuw.h

@@ -0,0 +1,2 @@
+RC = sext32((RA * RB) >> 32);
+

riscv/insns/mulhw.h

@@ -0,0 +1,2 @@
+RC = sext32((sreg_t(RA) * sreg_t(RB)) >> 32);
+

riscv/insns/mulw.h

@@ -0,0 +1,2 @@
+RC = sext32(RA * RB);
+

riscv/insns/rem.h

@@ -1,2 +1,2 @@
-RC = sext32(int32_t(RA) % int32_t(RB));
-
+require64;
+RC = sreg_t(RA) % sreg_t(RB);

riscv/insns/remu.h

@@ -1,2 +1,2 @@
-RC = sext32(uint32_t(RA) % uint32_t(RB));
-
+require64;
+RC = RA % RB;

riscv/insns/remuw.h

@@ -0,0 +1,2 @@
+RC = sext32(uint32_t(RA) % uint32_t(RB));
+

riscv/insns/remw.h

@@ -0,0 +1,2 @@
+RC = sext32(int32_t(RA) % int32_t(RB));
+

riscv/insns/sll.h

@@ -1 +1,2 @@
-RC = sext32(RB << SHAMT);
+require64;
+RC = RB << SHAMT;

riscv/insns/sllv.h

@@ -1 +1,2 @@
-RC = sext32(RB << (RA & 0x1F));
+require64;
+RC = RB << (RA & 0x3F);

riscv/insns/sllvw.h

@@ -0,0 +1 @@
+RC = sext32(RB << (RA & 0x1F));

riscv/insns/sllw.h

@@ -0,0 +1 @@
+RC = sext32(RB << SHAMT);

riscv/insns/sra.h

@@ -1 +1,2 @@
-RC = sext32(sreg_t(RB) >> SHAMT);
+require64;
+RC = sreg_t(RB) >> SHAMT;

riscv/insns/srav.h

@@ -1 +1,2 @@
-RC = sext32(sreg_t(RB) >> (RA & 0x1F));
+require64;
+RC = RB >> (RA & 0x3F);

riscv/insns/sravw.h

@@ -0,0 +1 @@
+RC = sext32(sreg_t(RB) >> (RA & 0x1F));

riscv/insns/sraw.h

@@ -0,0 +1 @@
+RC = sext32(sreg_t(RB) >> SHAMT);

riscv/insns/srl.h

@@ -1 +1,2 @@
-RC = sext32(RB >> SHAMT);
+require64;
+RC = RB >> SHAMT;

riscv/insns/srlv.h

@@ -1 +1,2 @@
-RC = sext32(RB >> (RA & 0x1F));
+require64;
+RC = RB >> (RA & 0x3F);

riscv/insns/srlvw.h

@@ -0,0 +1 @@
+RC = sext32(RB >> (RA & 0x1F));

riscv/insns/srlw.h

@@ -0,0 +1 @@
+RC = sext32(RB >> SHAMT);

riscv/insns/sub.h

@@ -1,2 +1,2 @@
-RC = sext32(RA - RB);
-
+require64;
+RC = RA - RB;

riscv/insns/subw.h

@@ -0,0 +1,2 @@
+RC = sext32(RA - RB);
+