diff --git a/riscv/decode.h b/riscv/decode.h
index 72b4a6b6..b5fad2d9 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -223,14 +223,56 @@ private:
 #define RVC_SP READ_REG(X_SP)
 
 // FPU macros
+#define READ_ZDINX_REG(reg) (xlen == 32 ? f64(READ_REG_PAIR(reg)) : f64(STATE.XPR[reg] & (uint64_t)-1))
+#define READ_FREG_H(reg) (p->extension_enabled(EXT_ZFINX) ? f16(STATE.XPR[reg] & (uint16_t)-1) : f16(READ_FREG(reg)))
+#define READ_FREG_F(reg) (p->extension_enabled(EXT_ZFINX) ? f32(STATE.XPR[reg] & (uint32_t)-1) : f32(READ_FREG(reg)))
+#define READ_FREG_D(reg) (p->extension_enabled(EXT_ZFINX) ? READ_ZDINX_REG(reg) : f64(READ_FREG(reg)))
 #define FRS1 READ_FREG(insn.rs1())
 #define FRS2 READ_FREG(insn.rs2())
 #define FRS3 READ_FREG(insn.rs3())
+#define FRS1_H READ_FREG_H(insn.rs1())
+#define FRS1_F READ_FREG_F(insn.rs1())
+#define FRS1_D READ_FREG_D(insn.rs1())
+#define FRS2_H READ_FREG_H(insn.rs2())
+#define FRS2_F READ_FREG_F(insn.rs2())
+#define FRS2_D READ_FREG_D(insn.rs2())
+#define FRS3_H READ_FREG_H(insn.rs3())
+#define FRS3_F READ_FREG_F(insn.rs3())
+#define FRS3_D READ_FREG_D(insn.rs3())
 #define dirty_fp_state  STATE.sstatus->dirty(SSTATUS_FS)
 #define dirty_ext_state STATE.sstatus->dirty(SSTATUS_XS)
 #define dirty_vs_state  STATE.sstatus->dirty(SSTATUS_VS)
 #define DO_WRITE_FREG(reg, value) (STATE.FPR.write(reg, value), dirty_fp_state)
 #define WRITE_FRD(value) WRITE_FREG(insn.rd(), value)
+#define WRITE_FRD_H(value) \
+do { \
+  if (p->extension_enabled(EXT_ZFINX)) \
+    WRITE_REG(insn.rd(), sext_xlen((int16_t)((value).v))); \
+  else { \
+    WRITE_FRD(value); \
+  } \
+} while(0)
+#define WRITE_FRD_F(value) \
+do { \
+  if (p->extension_enabled(EXT_ZFINX)) \
+    WRITE_REG(insn.rd(), sext_xlen((value).v)); \
+  else { \
+    WRITE_FRD(value); \
+  } \
+} while(0)
+#define WRITE_FRD_D(value) \
+do { \
+  if (p->extension_enabled(EXT_ZFINX)) { \
+    if (xlen == 32) { \
+      uint64_t val = (value).v; \
+      WRITE_RD_PAIR(val); \
+    } else { \
+      WRITE_REG(insn.rd(), (value).v); \
+    } \
+  } else { \
+    WRITE_FRD(value); \
+  } \
+} while(0)
  
 #define SHAMT (insn.i_imm() & 0x3F)
 #define BRANCH_TARGET (pc + insn.sb_imm())
diff --git a/riscv/insns/fadd_d.h b/riscv/insns/fadd_d.h
index 4a436e24..9bfff5fb 100644
--- a/riscv/insns/fadd_d.h
+++ b/riscv/insns/fadd_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_add(f64(FRS1), f64(FRS2)));
+WRITE_FRD_D(f64_add(FRS1_D, FRS2_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fadd_h.h b/riscv/insns/fadd_h.h
index 2b646ae7..f57e5fa7 100644
--- a/riscv/insns/fadd_h.h
+++ b/riscv/insns/fadd_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_add(f16(FRS1), f16(FRS2)));
+WRITE_FRD_H(f16_add(FRS1_H, FRS2_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fadd_s.h b/riscv/insns/fadd_s.h
index cc18d58c..7a40b1bf 100644
--- a/riscv/insns/fadd_s.h
+++ b/riscv/insns/fadd_s.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_add(f32(FRS1), f32(FRS2)));
+WRITE_FRD_F(f32_add(FRS1_F, FRS2_F));
 set_fp_exceptions;
diff --git a/riscv/insns/fclass_d.h b/riscv/insns/fclass_d.h
index 9456123d..a3550629 100644
--- a/riscv/insns/fclass_d.h
+++ b/riscv/insns/fclass_d.h
@@ -1,3 +1,3 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-WRITE_RD(f64_classify(f64(FRS1)));
+WRITE_RD(f64_classify(FRS1_D));
diff --git a/riscv/insns/fclass_h.h b/riscv/insns/fclass_h.h
index 066a2d24..2638ac8d 100644
--- a/riscv/insns/fclass_h.h
+++ b/riscv/insns/fclass_h.h
@@ -1,3 +1,3 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_RD(f16_classify(f16(FRS1)));
+WRITE_RD(f16_classify(FRS1_H));
diff --git a/riscv/insns/fclass_s.h b/riscv/insns/fclass_s.h
index a392db88..3d529adc 100644
--- a/riscv/insns/fclass_s.h
+++ b/riscv/insns/fclass_s.h
@@ -1,3 +1,3 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-WRITE_RD(f32_classify(f32(FRS1)));
+WRITE_RD(f32_classify(FRS1_F));
diff --git a/riscv/insns/fcvt_d_h.h b/riscv/insns/fcvt_d_h.h
index 04e9ff4e..061a2710 100644
--- a/riscv/insns/fcvt_d_h.h
+++ b/riscv/insns/fcvt_d_h.h
@@ -1,6 +1,6 @@
-require_extension(EXT_ZFHMIN);
-require_extension('D');
+require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN);
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_to_f64(f16(FRS1)));
+WRITE_FRD_D(f16_to_f64(FRS1_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_d_l.h b/riscv/insns/fcvt_d_l.h
index 08716cff..7788f1f0 100644
--- a/riscv/insns/fcvt_d_l.h
+++ b/riscv/insns/fcvt_d_l.h
@@ -1,6 +1,6 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i64_to_f64(RS1));
+WRITE_FRD_D(i64_to_f64(RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_d_lu.h b/riscv/insns/fcvt_d_lu.h
index 306d7fed..edb694f7 100644
--- a/riscv/insns/fcvt_d_lu.h
+++ b/riscv/insns/fcvt_d_lu.h
@@ -1,6 +1,6 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui64_to_f64(RS1));
+WRITE_FRD_D(ui64_to_f64(RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_d_s.h b/riscv/insns/fcvt_d_s.h
index 5f805b06..8039e946 100644
--- a/riscv/insns/fcvt_d_s.h
+++ b/riscv/insns/fcvt_d_s.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_to_f64(f32(FRS1)));
+WRITE_FRD_D(f32_to_f64(FRS1_F));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_d_w.h b/riscv/insns/fcvt_d_w.h
index 4c4861c1..e3375faf 100644
--- a/riscv/insns/fcvt_d_w.h
+++ b/riscv/insns/fcvt_d_w.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i32_to_f64((int32_t)RS1));
+WRITE_FRD_D(i32_to_f64((int32_t)RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_d_wu.h b/riscv/insns/fcvt_d_wu.h
index 1dbf218a..d903561f 100644
--- a/riscv/insns/fcvt_d_wu.h
+++ b/riscv/insns/fcvt_d_wu.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui32_to_f64((uint32_t)RS1));
+WRITE_FRD_D(ui32_to_f64((uint32_t)RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_h_d.h b/riscv/insns/fcvt_h_d.h
index e9987b7f..e06b1a55 100644
--- a/riscv/insns/fcvt_h_d.h
+++ b/riscv/insns/fcvt_h_d.h
@@ -1,6 +1,6 @@
-require_extension(EXT_ZFHMIN);
-require_extension('D');
+require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN);
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_to_f16(f64(FRS1)));
+WRITE_FRD_H(f64_to_f16(FRS1_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_h_l.h b/riscv/insns/fcvt_h_l.h
index 39178c2f..31e8a1e4 100644
--- a/riscv/insns/fcvt_h_l.h
+++ b/riscv/insns/fcvt_h_l.h
@@ -1,6 +1,6 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i64_to_f16(RS1));
+WRITE_FRD_H(i64_to_f16(RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_h_lu.h b/riscv/insns/fcvt_h_lu.h
index a872c480..189b1601 100644
--- a/riscv/insns/fcvt_h_lu.h
+++ b/riscv/insns/fcvt_h_lu.h
@@ -1,6 +1,6 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui64_to_f16(RS1));
+WRITE_FRD_H(ui64_to_f16(RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_h_s.h b/riscv/insns/fcvt_h_s.h
index ce39d814..57ba0059 100644
--- a/riscv/insns/fcvt_h_s.h
+++ b/riscv/insns/fcvt_h_s.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFHMIN);
+require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_to_f16(f32(FRS1)));
+WRITE_FRD_H(f32_to_f16(FRS1_F));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_h_w.h b/riscv/insns/fcvt_h_w.h
index c0824545..de4cbe56 100644
--- a/riscv/insns/fcvt_h_w.h
+++ b/riscv/insns/fcvt_h_w.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i32_to_f16((int32_t)RS1));
+WRITE_FRD_H(i32_to_f16((int32_t)RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_h_wu.h b/riscv/insns/fcvt_h_wu.h
index 9f2f5f6a..230c354f 100644
--- a/riscv/insns/fcvt_h_wu.h
+++ b/riscv/insns/fcvt_h_wu.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui32_to_f16((uint32_t)RS1));
+WRITE_FRD_H(ui32_to_f16((uint32_t)RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_l_d.h b/riscv/insns/fcvt_l_d.h
index c09e6c44..f2374d26 100644
--- a/riscv/insns/fcvt_l_d.h
+++ b/riscv/insns/fcvt_l_d.h
@@ -1,6 +1,6 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(f64_to_i64(f64(FRS1), RM, true));
+WRITE_RD(f64_to_i64(FRS1_D, RM, true));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_l_h.h b/riscv/insns/fcvt_l_h.h
index 5a1fea85..3b630276 100644
--- a/riscv/insns/fcvt_l_h.h
+++ b/riscv/insns/fcvt_l_h.h
@@ -1,6 +1,6 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(f16_to_i64(f16(FRS1), RM, true));
+WRITE_RD(f16_to_i64(FRS1_H, RM, true));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_l_s.h b/riscv/insns/fcvt_l_s.h
index 267e0eb8..d121a65c 100644
--- a/riscv/insns/fcvt_l_s.h
+++ b/riscv/insns/fcvt_l_s.h
@@ -1,6 +1,6 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(f32_to_i64(f32(FRS1), RM, true));
+WRITE_RD(f32_to_i64(FRS1_F, RM, true));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_lu_d.h b/riscv/insns/fcvt_lu_d.h
index 3a021204..939bc0e1 100644
--- a/riscv/insns/fcvt_lu_d.h
+++ b/riscv/insns/fcvt_lu_d.h
@@ -1,6 +1,6 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(f64_to_ui64(f64(FRS1), RM, true));
+WRITE_RD(f64_to_ui64(FRS1_D, RM, true));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_lu_h.h b/riscv/insns/fcvt_lu_h.h
index f1454c3e..d27f175e 100644
--- a/riscv/insns/fcvt_lu_h.h
+++ b/riscv/insns/fcvt_lu_h.h
@@ -1,6 +1,6 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(f16_to_ui64(f16(FRS1), RM, true));
+WRITE_RD(f16_to_ui64(FRS1_H, RM, true));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_lu_s.h b/riscv/insns/fcvt_lu_s.h
index 94115a3f..69c95ef0 100644
--- a/riscv/insns/fcvt_lu_s.h
+++ b/riscv/insns/fcvt_lu_s.h
@@ -1,6 +1,6 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(f32_to_ui64(f32(FRS1), RM, true));
+WRITE_RD(f32_to_ui64(FRS1_F, RM, true));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_d.h b/riscv/insns/fcvt_s_d.h
index 40333359..f3cd26e9 100644
--- a/riscv/insns/fcvt_s_d.h
+++ b/riscv/insns/fcvt_s_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_to_f32(f64(FRS1)));
+WRITE_FRD_F(f64_to_f32(FRS1_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_h.h b/riscv/insns/fcvt_s_h.h
index 22cdd728..346440a9 100644
--- a/riscv/insns/fcvt_s_h.h
+++ b/riscv/insns/fcvt_s_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFHMIN);
+require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_to_f32(f16(FRS1)));
+WRITE_FRD_F(f16_to_f32(FRS1_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_l.h b/riscv/insns/fcvt_s_l.h
index 9abcc805..1d096d2c 100644
--- a/riscv/insns/fcvt_s_l.h
+++ b/riscv/insns/fcvt_s_l.h
@@ -1,6 +1,6 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i64_to_f32(RS1));
+WRITE_FRD_F(i64_to_f32(RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_lu.h b/riscv/insns/fcvt_s_lu.h
index 70c676ed..e4e84cf4 100644
--- a/riscv/insns/fcvt_s_lu.h
+++ b/riscv/insns/fcvt_s_lu.h
@@ -1,6 +1,6 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui64_to_f32(RS1));
+WRITE_FRD_F(ui64_to_f32(RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_w.h b/riscv/insns/fcvt_s_w.h
index 1ddabd87..75c87db5 100644
--- a/riscv/insns/fcvt_s_w.h
+++ b/riscv/insns/fcvt_s_w.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i32_to_f32((int32_t)RS1));
+WRITE_FRD_F(i32_to_f32((int32_t)RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_wu.h b/riscv/insns/fcvt_s_wu.h
index c1394c3f..ec90fad9 100644
--- a/riscv/insns/fcvt_s_wu.h
+++ b/riscv/insns/fcvt_s_wu.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui32_to_f32((uint32_t)RS1));
+WRITE_FRD_F(ui32_to_f32((uint32_t)RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_w_d.h b/riscv/insns/fcvt_w_d.h
index 28eb2456..a839f4ba 100644
--- a/riscv/insns/fcvt_w_d.h
+++ b/riscv/insns/fcvt_w_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(sext32(f64_to_i32(f64(FRS1), RM, true)));
+WRITE_RD(sext32(f64_to_i32(FRS1_D, RM, true)));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_w_h.h b/riscv/insns/fcvt_w_h.h
index fe8bb48f..97e49a55 100644
--- a/riscv/insns/fcvt_w_h.h
+++ b/riscv/insns/fcvt_w_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(sext32(f16_to_i32(f16(FRS1), RM, true)));
+WRITE_RD(sext32(f16_to_i32(FRS1_H, RM, true)));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_w_s.h b/riscv/insns/fcvt_w_s.h
index d30f1b44..6aeb5101 100644
--- a/riscv/insns/fcvt_w_s.h
+++ b/riscv/insns/fcvt_w_s.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(sext32(f32_to_i32(f32(FRS1), RM, true)));
+WRITE_RD(sext32(f32_to_i32(FRS1_F, RM, true)));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_wu_d.h b/riscv/insns/fcvt_wu_d.h
index 5cdc004c..906f003f 100644
--- a/riscv/insns/fcvt_wu_d.h
+++ b/riscv/insns/fcvt_wu_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(sext32(f64_to_ui32(f64(FRS1), RM, true)));
+WRITE_RD(sext32(f64_to_ui32(FRS1_D, RM, true)));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_wu_h.h b/riscv/insns/fcvt_wu_h.h
index bf6648d3..ce111438 100644
--- a/riscv/insns/fcvt_wu_h.h
+++ b/riscv/insns/fcvt_wu_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(sext32(f16_to_ui32(f16(FRS1), RM, true)));
+WRITE_RD(sext32(f16_to_ui32(FRS1_H, RM, true)));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_wu_s.h b/riscv/insns/fcvt_wu_s.h
index 034d6816..a8b84557 100644
--- a/riscv/insns/fcvt_wu_s.h
+++ b/riscv/insns/fcvt_wu_s.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(sext32(f32_to_ui32(f32(FRS1), RM, true)));
+WRITE_RD(sext32(f32_to_ui32(FRS1_F, RM, true)));
 set_fp_exceptions;
diff --git a/riscv/insns/fdiv_d.h b/riscv/insns/fdiv_d.h
index ae7911ae..990afca0 100644
--- a/riscv/insns/fdiv_d.h
+++ b/riscv/insns/fdiv_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_div(f64(FRS1), f64(FRS2)));
+WRITE_FRD_D(f64_div(FRS1_D, FRS2_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fdiv_h.h b/riscv/insns/fdiv_h.h
index a169eae8..91c518b4 100644
--- a/riscv/insns/fdiv_h.h
+++ b/riscv/insns/fdiv_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_div(f16(FRS1), f16(FRS2)));
+WRITE_FRD_H(f16_div(FRS1_H, FRS2_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fdiv_s.h b/riscv/insns/fdiv_s.h
index c74ff041..180b41dd 100644
--- a/riscv/insns/fdiv_s.h
+++ b/riscv/insns/fdiv_s.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_div(f32(FRS1), f32(FRS2)));
+WRITE_FRD_F(f32_div(FRS1_F, FRS2_F));
 set_fp_exceptions;
diff --git a/riscv/insns/feq_d.h b/riscv/insns/feq_d.h
index 541ed5bb..9585bad7 100644
--- a/riscv/insns/feq_d.h
+++ b/riscv/insns/feq_d.h
@@ -1,4 +1,4 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-WRITE_RD(f64_eq(f64(FRS1), f64(FRS2)));
+WRITE_RD(f64_eq(FRS1_D, FRS2_D));
 set_fp_exceptions;
diff --git a/riscv/insns/feq_h.h b/riscv/insns/feq_h.h
index 47e75a5b..5988db90 100644
--- a/riscv/insns/feq_h.h
+++ b/riscv/insns/feq_h.h
@@ -1,4 +1,4 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_RD(f16_eq(f16(FRS1), f16(FRS2)));
+WRITE_RD(f16_eq(FRS1_H, FRS2_H));
 set_fp_exceptions;
diff --git a/riscv/insns/feq_s.h b/riscv/insns/feq_s.h
index 489bea69..97b57c2e 100644
--- a/riscv/insns/feq_s.h
+++ b/riscv/insns/feq_s.h
@@ -1,4 +1,4 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-WRITE_RD(f32_eq(f32(FRS1), f32(FRS2)));
+WRITE_RD(f32_eq(FRS1_F, FRS2_F));
 set_fp_exceptions;
diff --git a/riscv/insns/fle_d.h b/riscv/insns/fle_d.h
index 419a36fc..17b49320 100644
--- a/riscv/insns/fle_d.h
+++ b/riscv/insns/fle_d.h
@@ -1,4 +1,4 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-WRITE_RD(f64_le(f64(FRS1), f64(FRS2)));
+WRITE_RD(f64_le(FRS1_D, FRS2_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fle_h.h b/riscv/insns/fle_h.h
index 9fc59685..31ed8a75 100644
--- a/riscv/insns/fle_h.h
+++ b/riscv/insns/fle_h.h
@@ -1,4 +1,4 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_RD(f16_le(f16(FRS1), f16(FRS2)));
+WRITE_RD(f16_le(FRS1_H, FRS2_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fle_s.h b/riscv/insns/fle_s.h
index 5c0124ef..e26f0556 100644
--- a/riscv/insns/fle_s.h
+++ b/riscv/insns/fle_s.h
@@ -1,4 +1,4 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-WRITE_RD(f32_le(f32(FRS1), f32(FRS2)));
+WRITE_RD(f32_le(FRS1_F, FRS2_F));
 set_fp_exceptions;
diff --git a/riscv/insns/flt_d.h b/riscv/insns/flt_d.h
index 7176a961..5fb05724 100644
--- a/riscv/insns/flt_d.h
+++ b/riscv/insns/flt_d.h
@@ -1,4 +1,4 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-WRITE_RD(f64_lt(f64(FRS1), f64(FRS2)));
+WRITE_RD(f64_lt(FRS1_D, FRS2_D));
 set_fp_exceptions;
diff --git a/riscv/insns/flt_h.h b/riscv/insns/flt_h.h
index f516a38a..dd6bc79f 100644
--- a/riscv/insns/flt_h.h
+++ b/riscv/insns/flt_h.h
@@ -1,4 +1,4 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_RD(f16_lt(f16(FRS1), f16(FRS2)));
+WRITE_RD(f16_lt(FRS1_H, FRS2_H));
 set_fp_exceptions;
diff --git a/riscv/insns/flt_s.h b/riscv/insns/flt_s.h
index 40acc34b..2f50ed6c 100644
--- a/riscv/insns/flt_s.h
+++ b/riscv/insns/flt_s.h
@@ -1,4 +1,4 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-WRITE_RD(f32_lt(f32(FRS1), f32(FRS2)));
+WRITE_RD(f32_lt(FRS1_F, FRS2_F));
 set_fp_exceptions;
diff --git a/riscv/insns/fmadd_d.h b/riscv/insns/fmadd_d.h
index ab22bebb..07a8b255 100644
--- a/riscv/insns/fmadd_d.h
+++ b/riscv/insns/fmadd_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(FRS3)));
+WRITE_FRD_D(f64_mulAdd(FRS1_D, FRS2_D, FRS3_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fmadd_h.h b/riscv/insns/fmadd_h.h
index 6551de5e..5428897a 100644
--- a/riscv/insns/fmadd_h.h
+++ b/riscv/insns/fmadd_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_mulAdd(f16(FRS1), f16(FRS2), f16(FRS3)));
+WRITE_FRD_H(f16_mulAdd(FRS1_H, FRS2_H, FRS3_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fmadd_s.h b/riscv/insns/fmadd_s.h
index e919190c..5a72cf81 100644
--- a/riscv/insns/fmadd_s.h
+++ b/riscv/insns/fmadd_s.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(FRS3)));
+WRITE_FRD_F(f32_mulAdd(FRS1_F, FRS2_F, FRS3_F));
 set_fp_exceptions;
diff --git a/riscv/insns/fmax_d.h b/riscv/insns/fmax_d.h
index 11491f54..3e05b7e6 100644
--- a/riscv/insns/fmax_d.h
+++ b/riscv/insns/fmax_d.h
@@ -1,9 +1,9 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-bool greater = f64_lt_quiet(f64(FRS2), f64(FRS1)) ||
-               (f64_eq(f64(FRS2), f64(FRS1)) && (f64(FRS2).v & F64_SIGN));
-if (isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v))
-  WRITE_FRD(f64(defaultNaNF64UI));
+bool greater = f64_lt_quiet(FRS2_D, FRS1_D) ||
+              (f64_eq(FRS2_D, FRS1_D) && (FRS2_D.v & F64_SIGN));
+if (isNaNF64UI(FRS1_D.v) && isNaNF64UI(FRS2_D.v))
+  WRITE_FRD_D(f64(defaultNaNF64UI));
 else
-  WRITE_FRD(greater || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
+  WRITE_FRD_D((greater || isNaNF64UI(FRS2_D.v) ? FRS1_D : FRS2_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fmax_h.h b/riscv/insns/fmax_h.h
index 3d4c40eb..c8642584 100644
--- a/riscv/insns/fmax_h.h
+++ b/riscv/insns/fmax_h.h
@@ -1,4 +1,4 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_FRD(f16_max(f16(FRS1), f16(FRS2)));
+WRITE_FRD_H(f16_max(FRS1_H, FRS2_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fmax_s.h b/riscv/insns/fmax_s.h
index 41d8f921..17d8b3c8 100644
--- a/riscv/insns/fmax_s.h
+++ b/riscv/insns/fmax_s.h
@@ -1,9 +1,9 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-bool greater = f32_lt_quiet(f32(FRS2), f32(FRS1)) ||
-               (f32_eq(f32(FRS2), f32(FRS1)) && (f32(FRS2).v & F32_SIGN));
-if (isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v))
-  WRITE_FRD(f32(defaultNaNF32UI));
+bool greater = f32_lt_quiet(FRS2_F, FRS1_F) ||
+               (f32_eq(FRS2_F, FRS1_F) && (FRS2_F.v & F32_SIGN));
+if (isNaNF32UI(FRS1_F.v) && isNaNF32UI(FRS2_F.v))
+  WRITE_FRD_F(f32(defaultNaNF32UI));
 else
-  WRITE_FRD(greater || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
+  WRITE_FRD_F((greater || isNaNF32UI(FRS2_F.v) ? FRS1_F : FRS2_F));
 set_fp_exceptions;
diff --git a/riscv/insns/fmin_d.h b/riscv/insns/fmin_d.h
index 5cf349d4..f60a73e7 100644
--- a/riscv/insns/fmin_d.h
+++ b/riscv/insns/fmin_d.h
@@ -1,9 +1,9 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-bool less = f64_lt_quiet(f64(FRS1), f64(FRS2)) ||
-            (f64_eq(f64(FRS1), f64(FRS2)) && (f64(FRS1).v & F64_SIGN));
-if (isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v))
-  WRITE_FRD(f64(defaultNaNF64UI));
+bool less = f64_lt_quiet(FRS1_D, FRS2_D) ||
+            (f64_eq(FRS1_D, FRS2_D) && (FRS1_D.v & F64_SIGN));
+if (isNaNF64UI(FRS1_D.v) && isNaNF64UI(FRS2_D.v))
+  WRITE_FRD_D(f64(defaultNaNF64UI));
 else
-  WRITE_FRD(less || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
+  WRITE_FRD_D((less || isNaNF64UI(FRS2_D.v) ? FRS1_D : FRS2_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fmin_h.h b/riscv/insns/fmin_h.h
index 5fb1404f..cd02f20e 100644
--- a/riscv/insns/fmin_h.h
+++ b/riscv/insns/fmin_h.h
@@ -1,4 +1,4 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_FRD(f16_min(f16(FRS1), f16(FRS2)));
+WRITE_FRD_H(f16_min(FRS1_H, FRS2_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fmin_s.h b/riscv/insns/fmin_s.h
index 19e11938..476a5860 100644
--- a/riscv/insns/fmin_s.h
+++ b/riscv/insns/fmin_s.h
@@ -1,9 +1,9 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-bool less = f32_lt_quiet(f32(FRS1), f32(FRS2)) ||
-            (f32_eq(f32(FRS1), f32(FRS2)) && (f32(FRS1).v & F32_SIGN));
-if (isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v))
-  WRITE_FRD(f32(defaultNaNF32UI));
+bool less = f32_lt_quiet(FRS1_F, FRS2_F) ||
+            (f32_eq(FRS1_F, FRS2_F) && (FRS1_F.v & F32_SIGN));
+if (isNaNF32UI(FRS1_F.v) && isNaNF32UI(FRS2_F.v))
+  WRITE_FRD_F(f32(defaultNaNF32UI));
 else
-  WRITE_FRD(less || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
+  WRITE_FRD_F((less || isNaNF32UI(FRS2_F.v) ? FRS1_F : FRS2_F));
 set_fp_exceptions;
diff --git a/riscv/insns/fmsub_d.h b/riscv/insns/fmsub_d.h
index 5b5bc0f7..1a7d7847 100644
--- a/riscv/insns/fmsub_d.h
+++ b/riscv/insns/fmsub_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(f64(FRS3).v ^ F64_SIGN)));
+WRITE_FRD_D(f64_mulAdd(FRS1_D, FRS2_D, f64(FRS3_D.v ^ F64_SIGN)));
 set_fp_exceptions;
diff --git a/riscv/insns/fmsub_h.h b/riscv/insns/fmsub_h.h
index 934291fc..dc6a8e6c 100644
--- a/riscv/insns/fmsub_h.h
+++ b/riscv/insns/fmsub_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_mulAdd(f16(FRS1), f16(FRS2), f16(f16(FRS3).v ^ F16_SIGN)));
+WRITE_FRD_H(f16_mulAdd(FRS1_H, FRS2_H, f16(FRS3_H.v ^ F16_SIGN)));
 set_fp_exceptions;
diff --git a/riscv/insns/fmsub_s.h b/riscv/insns/fmsub_s.h
index d46c887e..179cc2f6 100644
--- a/riscv/insns/fmsub_s.h
+++ b/riscv/insns/fmsub_s.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(f32(FRS3).v ^ F32_SIGN)));
+WRITE_FRD_F(f32_mulAdd(FRS1_F, FRS2_F, f32(FRS3_F.v ^ F32_SIGN)));
 set_fp_exceptions;
diff --git a/riscv/insns/fmul_d.h b/riscv/insns/fmul_d.h
index 9189d8d9..e5caa34c 100644
--- a/riscv/insns/fmul_d.h
+++ b/riscv/insns/fmul_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_mul(f64(FRS1), f64(FRS2)));
+WRITE_FRD_D(f64_mul(FRS1_D, FRS2_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fmul_h.h b/riscv/insns/fmul_h.h
index 0152df8f..dc7f9c47 100644
--- a/riscv/insns/fmul_h.h
+++ b/riscv/insns/fmul_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_mul(f16(FRS1), f16(FRS2)));
+WRITE_FRD_H(f16_mul(FRS1_H, FRS2_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fmul_s.h b/riscv/insns/fmul_s.h
index 145d5ce4..9cf30b4b 100644
--- a/riscv/insns/fmul_s.h
+++ b/riscv/insns/fmul_s.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mul(f32(FRS1), f32(FRS2)));
+WRITE_FRD_F(f32_mul(FRS1_F, FRS2_F));
 set_fp_exceptions;
diff --git a/riscv/insns/fnmadd_d.h b/riscv/insns/fnmadd_d.h
index e8dd7432..a2a14e9c 100644
--- a/riscv/insns/fnmadd_d.h
+++ b/riscv/insns/fnmadd_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_mulAdd(f64(f64(FRS1).v ^ F64_SIGN), f64(FRS2), f64(f64(FRS3).v ^ F64_SIGN)));
+WRITE_FRD_D(f64_mulAdd(f64(FRS1_D.v ^ F64_SIGN), FRS2_D, f64(FRS3_D.v ^ F64_SIGN)));
 set_fp_exceptions;
diff --git a/riscv/insns/fnmadd_h.h b/riscv/insns/fnmadd_h.h
index e4c619e7..b1ca2832 100644
--- a/riscv/insns/fnmadd_h.h
+++ b/riscv/insns/fnmadd_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_mulAdd(f16(f16(FRS1).v ^ F16_SIGN), f16(FRS2), f16(f16(FRS3).v ^ F16_SIGN)));
+WRITE_FRD_H(f16_mulAdd(f16(FRS1_H.v ^ F16_SIGN), FRS2_H, f16(FRS3_H.v ^ F16_SIGN)));
 set_fp_exceptions;
diff --git a/riscv/insns/fnmadd_s.h b/riscv/insns/fnmadd_s.h
index 1c2996e3..683257ad 100644
--- a/riscv/insns/fnmadd_s.h
+++ b/riscv/insns/fnmadd_s.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(f32(FRS1).v ^ F32_SIGN), f32(FRS2), f32(f32(FRS3).v ^ F32_SIGN)));
+WRITE_FRD_F(f32_mulAdd(f32(FRS1_F.v ^ F32_SIGN), FRS2_F, f32(FRS3_F.v ^ F32_SIGN)));
 set_fp_exceptions;
diff --git a/riscv/insns/fnmsub_d.h b/riscv/insns/fnmsub_d.h
index c29a0b93..9352c3fd 100644
--- a/riscv/insns/fnmsub_d.h
+++ b/riscv/insns/fnmsub_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_mulAdd(f64(f64(FRS1).v ^ F64_SIGN), f64(FRS2), f64(FRS3)));
+WRITE_FRD_D(f64_mulAdd(f64(FRS1_D.v ^ F64_SIGN), FRS2_D, FRS3_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fnmsub_h.h b/riscv/insns/fnmsub_h.h
index 0410c3bb..e05fcd1f 100644
--- a/riscv/insns/fnmsub_h.h
+++ b/riscv/insns/fnmsub_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_mulAdd(f16(f16(FRS1).v ^ F16_SIGN), f16(FRS2), f16(FRS3)));
+WRITE_FRD_H(f16_mulAdd(f16(FRS1_H.v ^ F16_SIGN), FRS2_H, FRS3_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fnmsub_s.h b/riscv/insns/fnmsub_s.h
index 4c61fc7c..b22b3db6 100644
--- a/riscv/insns/fnmsub_s.h
+++ b/riscv/insns/fnmsub_s.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(f32(FRS1).v ^ F32_SIGN), f32(FRS2), f32(FRS3)));
+WRITE_FRD_F(f32_mulAdd(f32(FRS1_F.v ^ F32_SIGN), FRS2_F, FRS3_F));
 set_fp_exceptions;
diff --git a/riscv/insns/fsgnj_d.h b/riscv/insns/fsgnj_d.h
index 78f9ce78..8f02fd11 100644
--- a/riscv/insns/fsgnj_d.h
+++ b/riscv/insns/fsgnj_d.h
@@ -1,3 +1,3 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-WRITE_FRD(fsgnj64(FRS1, FRS2, false, false));
+WRITE_FRD_D(fsgnj64(freg(FRS1_D), freg(FRS2_D), false, false));
diff --git a/riscv/insns/fsgnj_h.h b/riscv/insns/fsgnj_h.h
index 79d50f5f..080f27d8 100644
--- a/riscv/insns/fsgnj_h.h
+++ b/riscv/insns/fsgnj_h.h
@@ -1,3 +1,3 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_FRD(fsgnj16(FRS1, FRS2, false, false));
+WRITE_FRD_H(fsgnj16(freg(FRS1_H), freg(FRS2_H), false, false));
diff --git a/riscv/insns/fsgnj_s.h b/riscv/insns/fsgnj_s.h
index c1a70cb7..ea511b89 100644
--- a/riscv/insns/fsgnj_s.h
+++ b/riscv/insns/fsgnj_s.h
@@ -1,3 +1,3 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-WRITE_FRD(fsgnj32(FRS1, FRS2, false, false));
+WRITE_FRD_F(fsgnj32(freg(FRS1_F), freg(FRS2_F), false, false));
diff --git a/riscv/insns/fsgnjn_d.h b/riscv/insns/fsgnjn_d.h
index f02c3116..870a9793 100644
--- a/riscv/insns/fsgnjn_d.h
+++ b/riscv/insns/fsgnjn_d.h
@@ -1,3 +1,3 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-WRITE_FRD(fsgnj64(FRS1, FRS2, true, false));
+WRITE_FRD_D(fsgnj64(freg(FRS1_D), freg(FRS2_D), true, false));
diff --git a/riscv/insns/fsgnjn_h.h b/riscv/insns/fsgnjn_h.h
index ebb4ac9f..1d7bf03b 100644
--- a/riscv/insns/fsgnjn_h.h
+++ b/riscv/insns/fsgnjn_h.h
@@ -1,3 +1,3 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_FRD(fsgnj16(FRS1, FRS2, true, false));
+WRITE_FRD_H(fsgnj16(freg(FRS1_H), freg(FRS2_H), true, false));
\ No newline at end of file
diff --git a/riscv/insns/fsgnjn_q.h b/riscv/insns/fsgnjn_q.h
index 38c7bbff..dcf72355 100644
--- a/riscv/insns/fsgnjn_q.h
+++ b/riscv/insns/fsgnjn_q.h
@@ -1,3 +1,3 @@
 require_extension('Q');
 require_fp;
-WRITE_FRD(fsgnj128(FRS1, FRS2, true, false));
+WRITE_FRD(fsgnj128(FRS1, FRS2, true, false));
\ No newline at end of file
diff --git a/riscv/insns/fsgnjn_s.h b/riscv/insns/fsgnjn_s.h
index 35906d65..a0994b49 100644
--- a/riscv/insns/fsgnjn_s.h
+++ b/riscv/insns/fsgnjn_s.h
@@ -1,3 +1,3 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-WRITE_FRD(fsgnj32(FRS1, FRS2, true, false));
+WRITE_FRD_F(fsgnj32(freg(FRS1_F), freg(FRS2_F), true, false));
diff --git a/riscv/insns/fsgnjx_d.h b/riscv/insns/fsgnjx_d.h
index c1217371..25906f08 100644
--- a/riscv/insns/fsgnjx_d.h
+++ b/riscv/insns/fsgnjx_d.h
@@ -1,3 +1,3 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-WRITE_FRD(fsgnj64(FRS1, FRS2, false, true));
+WRITE_FRD_D(fsgnj64(freg(FRS1_D), freg(FRS2_D), false, true));
diff --git a/riscv/insns/fsgnjx_h.h b/riscv/insns/fsgnjx_h.h
index 93102695..1d29bb1f 100644
--- a/riscv/insns/fsgnjx_h.h
+++ b/riscv/insns/fsgnjx_h.h
@@ -1,3 +1,3 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_FRD(fsgnj16(FRS1, FRS2, false, true));
+WRITE_FRD_H(fsgnj16(freg(FRS1_H), freg(FRS2_H), false, true));
diff --git a/riscv/insns/fsgnjx_s.h b/riscv/insns/fsgnjx_s.h
index 4d5c624b..9bc07988 100644
--- a/riscv/insns/fsgnjx_s.h
+++ b/riscv/insns/fsgnjx_s.h
@@ -1,3 +1,3 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-WRITE_FRD(fsgnj32(FRS1, FRS2, false, true));
+WRITE_FRD_F(fsgnj32(freg(FRS1_F), freg(FRS2_F), false, true));
diff --git a/riscv/insns/fsqrt_d.h b/riscv/insns/fsqrt_d.h
index da138ba1..363b457f 100644
--- a/riscv/insns/fsqrt_d.h
+++ b/riscv/insns/fsqrt_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_sqrt(f64(FRS1)));
+WRITE_FRD_D(f64_sqrt(FRS1_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fsqrt_h.h b/riscv/insns/fsqrt_h.h
index 138d5727..fea429bd 100644
--- a/riscv/insns/fsqrt_h.h
+++ b/riscv/insns/fsqrt_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_sqrt(f16(FRS1)));
+WRITE_FRD_H(f16_sqrt(FRS1_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fsqrt_s.h b/riscv/insns/fsqrt_s.h
index 74768466..d44503a7 100644
--- a/riscv/insns/fsqrt_s.h
+++ b/riscv/insns/fsqrt_s.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_sqrt(f32(FRS1)));
+WRITE_FRD_F(f32_sqrt(FRS1_F));
 set_fp_exceptions;
diff --git a/riscv/insns/fsub_d.h b/riscv/insns/fsub_d.h
index 1418a063..4f8bf509 100644
--- a/riscv/insns/fsub_d.h
+++ b/riscv/insns/fsub_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_sub(f64(FRS1), f64(FRS2)));
+WRITE_FRD_D(f64_sub(FRS1_D, FRS2_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fsub_h.h b/riscv/insns/fsub_h.h
index 43b51cc2..f7006fb0 100644
--- a/riscv/insns/fsub_h.h
+++ b/riscv/insns/fsub_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_sub(f16(FRS1), f16(FRS2)));
+WRITE_FRD_H(f16_sub(FRS1_H, FRS2_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fsub_s.h b/riscv/insns/fsub_s.h
index f6183ea0..1a33ffdb 100644
--- a/riscv/insns/fsub_s.h
+++ b/riscv/insns/fsub_s.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_sub(f32(FRS1), f32(FRS2)));
+WRITE_FRD_F(f32_sub(FRS1_F, FRS2_F));
 set_fp_exceptions;
diff --git a/riscv/insns/vfslide1down_vf.h b/riscv/insns/vfslide1down_vf.h
index 66eeaccb..40f3c181 100644
--- a/riscv/insns/vfslide1down_vf.h
+++ b/riscv/insns/vfslide1down_vf.h
@@ -23,13 +23,13 @@ if (i != vl - 1) {
 } else {
   switch (P.VU.vsew) {
     case e16:
-      P.VU.elt<float16_t>(rd_num, vl - 1, true) = f16(FRS1);
+      P.VU.elt<float16_t>(rd_num, vl - 1, true) = FRS1_H;
       break;
     case e32:
-      P.VU.elt<float32_t>(rd_num, vl - 1, true) = f32(FRS1);
+      P.VU.elt<float32_t>(rd_num, vl - 1, true) = FRS1_F;
       break;
     case e64:
-      P.VU.elt<float64_t>(rd_num, vl - 1, true) = f64(FRS1);
+      P.VU.elt<float64_t>(rd_num, vl - 1, true) = FRS1_D;
       break;
   }
 }
diff --git a/riscv/insns/vfslide1up_vf.h b/riscv/insns/vfslide1up_vf.h
index b9c2817c..4e4e499a 100644
--- a/riscv/insns/vfslide1up_vf.h
+++ b/riscv/insns/vfslide1up_vf.h
@@ -23,13 +23,13 @@ if (i != 0) {
 } else {
   switch (P.VU.vsew) {
     case e16:
-      P.VU.elt<float16_t>(rd_num, 0, true) = f16(FRS1);
+      P.VU.elt<float16_t>(rd_num, 0, true) = FRS1_H;
       break;
     case e32:
-      P.VU.elt<float32_t>(rd_num, 0, true) = f32(FRS1);
+      P.VU.elt<float32_t>(rd_num, 0, true) = FRS1_F;
       break;
     case e64:
-      P.VU.elt<float64_t>(rd_num, 0, true) = f64(FRS1);
+      P.VU.elt<float64_t>(rd_num, 0, true) = FRS1_D;
       break;
   }
 }
diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h
index 1a2a7343..9ff383cb 100644
--- a/riscv/v_ext_macros.h
+++ b/riscv/v_ext_macros.h
@@ -1802,7 +1802,7 @@ reg_t index[P.VU.vlmax]; \
     case e16: { \
       float32_t &vd = P.VU.elt<float32_t>(rd_num, i, true); \
       float32_t vs2 = f16_to_f32(P.VU.elt<float16_t>(rs2_num, i)); \
-      float32_t rs1 = f16_to_f32(f16(READ_FREG(rs1_num))); \
+      float32_t rs1 = f16_to_f32(FRS1_H); \
       BODY16; \
       set_fp_exceptions; \
       break; \
@@ -1810,7 +1810,7 @@ reg_t index[P.VU.vlmax]; \
     case e32: { \
       float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \
       float64_t vs2 = f32_to_f64(P.VU.elt<float32_t>(rs2_num, i)); \
-      float64_t rs1 = f32_to_f64(f32(READ_FREG(rs1_num))); \
+      float64_t rs1 = f32_to_f64(FRS1_F); \
       BODY32; \
       set_fp_exceptions; \
       break; \
@@ -1856,7 +1856,7 @@ reg_t index[P.VU.vlmax]; \
     case e16: { \
       float32_t &vd = P.VU.elt<float32_t>(rd_num, i, true); \
       float32_t vs2 = P.VU.elt<float32_t>(rs2_num, i); \
-      float32_t rs1 = f16_to_f32(f16(READ_FREG(rs1_num))); \
+      float32_t rs1 = f16_to_f32(FRS1_H); \
       BODY16; \
       set_fp_exceptions; \
       break; \
@@ -1864,7 +1864,7 @@ reg_t index[P.VU.vlmax]; \
     case e32: { \
       float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \
       float64_t vs2 = P.VU.elt<float64_t>(rs2_num, i); \
-      float64_t rs1 = f32_to_f64(f32(READ_FREG(rs1_num))); \
+      float64_t rs1 = f32_to_f64(FRS1_F); \
       BODY32; \
       set_fp_exceptions; \
       break; \