Modify F/D/Zfh instructions to add support for Zfinx/Zdinx/Zhinx{min} instructions

change the extention check for F/D/Zfh instructions

modify the F/D/Zfh instructions to read X regs when enable Zfinx

Co-authored-by: wangmeng <shusheng8495@hotmail.com>

riscv/decode.h

@@ -223,14 +223,56 @@ private:
 #define RVC_SP READ_REG(X_SP)
 
 // FPU macros
+#define READ_ZDINX_REG(reg) (xlen == 32 ? f64(READ_REG_PAIR(reg)) : f64(STATE.XPR[reg] & (uint64_t)-1))
+#define READ_FREG_H(reg) (p->extension_enabled(EXT_ZFINX) ? f16(STATE.XPR[reg] & (uint16_t)-1) : f16(READ_FREG(reg)))
+#define READ_FREG_F(reg) (p->extension_enabled(EXT_ZFINX) ? f32(STATE.XPR[reg] & (uint32_t)-1) : f32(READ_FREG(reg)))
+#define READ_FREG_D(reg) (p->extension_enabled(EXT_ZFINX) ? READ_ZDINX_REG(reg) : f64(READ_FREG(reg)))
 #define FRS1 READ_FREG(insn.rs1())
 #define FRS2 READ_FREG(insn.rs2())
 #define FRS3 READ_FREG(insn.rs3())
+#define FRS1_H READ_FREG_H(insn.rs1())
+#define FRS1_F READ_FREG_F(insn.rs1())
+#define FRS1_D READ_FREG_D(insn.rs1())
+#define FRS2_H READ_FREG_H(insn.rs2())
+#define FRS2_F READ_FREG_F(insn.rs2())
+#define FRS2_D READ_FREG_D(insn.rs2())
+#define FRS3_H READ_FREG_H(insn.rs3())
+#define FRS3_F READ_FREG_F(insn.rs3())
+#define FRS3_D READ_FREG_D(insn.rs3())
 #define dirty_fp_state  STATE.sstatus->dirty(SSTATUS_FS)
 #define dirty_ext_state STATE.sstatus->dirty(SSTATUS_XS)
 #define dirty_vs_state  STATE.sstatus->dirty(SSTATUS_VS)
 #define DO_WRITE_FREG(reg, value) (STATE.FPR.write(reg, value), dirty_fp_state)
 #define WRITE_FRD(value) WRITE_FREG(insn.rd(), value)
+#define WRITE_FRD_H(value) \
+do { \
+  if (p->extension_enabled(EXT_ZFINX)) \
+    WRITE_REG(insn.rd(), sext_xlen((int16_t)((value).v))); \
+  else { \
+    WRITE_FRD(value); \
+  } \
+} while(0)
+#define WRITE_FRD_F(value) \
+do { \
+  if (p->extension_enabled(EXT_ZFINX)) \
+    WRITE_REG(insn.rd(), sext_xlen((value).v)); \
+  else { \
+    WRITE_FRD(value); \
+  } \
+} while(0)
+#define WRITE_FRD_D(value) \
+do { \
+  if (p->extension_enabled(EXT_ZFINX)) { \
+    if (xlen == 32) { \
+      uint64_t val = (value).v; \
+      WRITE_RD_PAIR(val); \
+    } else { \
+      WRITE_REG(insn.rd(), (value).v); \
+    } \
+  } else { \
+    WRITE_FRD(value); \
+  } \
+} while(0)
  
 #define SHAMT (insn.i_imm() & 0x3F)
 #define BRANCH_TARGET (pc + insn.sb_imm())

riscv/insns/fadd_d.h

@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_add(f64(FRS1), f64(FRS2)));
+WRITE_FRD_D(f64_add(FRS1_D, FRS2_D));
 set_fp_exceptions;

riscv/insns/fadd_h.h

@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_add(f16(FRS1), f16(FRS2)));
+WRITE_FRD_H(f16_add(FRS1_H, FRS2_H));
 set_fp_exceptions;

riscv/insns/fadd_s.h

@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_add(f32(FRS1), f32(FRS2)));
+WRITE_FRD_F(f32_add(FRS1_F, FRS2_F));
 set_fp_exceptions;

riscv/insns/fclass_d.h

@@ -1,3 +1,3 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-WRITE_RD(f64_classify(f64(FRS1)));
+WRITE_RD(f64_classify(FRS1_D));

riscv/insns/fclass_h.h

@@ -1,3 +1,3 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_RD(f16_classify(f16(FRS1)));
+WRITE_RD(f16_classify(FRS1_H));

riscv/insns/fclass_s.h

@@ -1,3 +1,3 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-WRITE_RD(f32_classify(f32(FRS1)));
+WRITE_RD(f32_classify(FRS1_F));

riscv/insns/fcvt_d_h.h

@@ -1,6 +1,6 @@
-require_extension(EXT_ZFHMIN);
-require_extension('D');
+require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN);
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_to_f64(f16(FRS1)));
+WRITE_FRD_D(f16_to_f64(FRS1_H));
 set_fp_exceptions;

riscv/insns/fcvt_d_l.h

@@ -1,6 +1,6 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i64_to_f64(RS1));
+WRITE_FRD_D(i64_to_f64(RS1));
 set_fp_exceptions;

riscv/insns/fcvt_d_lu.h

@@ -1,6 +1,6 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui64_to_f64(RS1));
+WRITE_FRD_D(ui64_to_f64(RS1));
 set_fp_exceptions;

riscv/insns/fcvt_d_s.h

@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_to_f64(f32(FRS1)));
+WRITE_FRD_D(f32_to_f64(FRS1_F));
 set_fp_exceptions;

riscv/insns/fcvt_d_w.h

@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i32_to_f64((int32_t)RS1));
+WRITE_FRD_D(i32_to_f64((int32_t)RS1));
 set_fp_exceptions;

riscv/insns/fcvt_d_wu.h

@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui32_to_f64((uint32_t)RS1));
+WRITE_FRD_D(ui32_to_f64((uint32_t)RS1));
 set_fp_exceptions;

riscv/insns/fcvt_h_d.h

@@ -1,6 +1,6 @@
-require_extension(EXT_ZFHMIN);
-require_extension('D');
+require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN);
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_to_f16(f64(FRS1)));
+WRITE_FRD_H(f64_to_f16(FRS1_D));
 set_fp_exceptions;

riscv/insns/fcvt_h_l.h

@@ -1,6 +1,6 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i64_to_f16(RS1));
+WRITE_FRD_H(i64_to_f16(RS1));
 set_fp_exceptions;

riscv/insns/fcvt_h_lu.h

@@ -1,6 +1,6 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui64_to_f16(RS1));
+WRITE_FRD_H(ui64_to_f16(RS1));
 set_fp_exceptions;

riscv/insns/fcvt_h_s.h

@@ -1,5 +1,5 @@
-require_extension(EXT_ZFHMIN);
+require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_to_f16(f32(FRS1)));
+WRITE_FRD_H(f32_to_f16(FRS1_F));
 set_fp_exceptions;

riscv/insns/fcvt_h_w.h

@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i32_to_f16((int32_t)RS1));
+WRITE_FRD_H(i32_to_f16((int32_t)RS1));
 set_fp_exceptions;

riscv/insns/fcvt_h_wu.h

@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui32_to_f16((uint32_t)RS1));
+WRITE_FRD_H(ui32_to_f16((uint32_t)RS1));
 set_fp_exceptions;

riscv/insns/fcvt_l_d.h

@@ -1,6 +1,6 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(f64_to_i64(f64(FRS1), RM, true));
+WRITE_RD(f64_to_i64(FRS1_D, RM, true));
 set_fp_exceptions;

riscv/insns/fcvt_l_h.h

@@ -1,6 +1,6 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(f16_to_i64(f16(FRS1), RM, true));
+WRITE_RD(f16_to_i64(FRS1_H, RM, true));
 set_fp_exceptions;

riscv/insns/fcvt_l_s.h

@@ -1,6 +1,6 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(f32_to_i64(f32(FRS1), RM, true));
+WRITE_RD(f32_to_i64(FRS1_F, RM, true));
 set_fp_exceptions;

riscv/insns/fcvt_lu_d.h

@@ -1,6 +1,6 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(f64_to_ui64(f64(FRS1), RM, true));
+WRITE_RD(f64_to_ui64(FRS1_D, RM, true));
 set_fp_exceptions;

riscv/insns/fcvt_lu_h.h

@@ -1,6 +1,6 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(f16_to_ui64(f16(FRS1), RM, true));
+WRITE_RD(f16_to_ui64(FRS1_H, RM, true));
 set_fp_exceptions;

riscv/insns/fcvt_lu_s.h

@@ -1,6 +1,6 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(f32_to_ui64(f32(FRS1), RM, true));
+WRITE_RD(f32_to_ui64(FRS1_F, RM, true));
 set_fp_exceptions;

riscv/insns/fcvt_s_d.h

@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_to_f32(f64(FRS1)));
+WRITE_FRD_F(f64_to_f32(FRS1_D));
 set_fp_exceptions;

riscv/insns/fcvt_s_h.h

@@ -1,5 +1,5 @@
-require_extension(EXT_ZFHMIN);
+require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_to_f32(f16(FRS1)));
+WRITE_FRD_F(f16_to_f32(FRS1_H));
 set_fp_exceptions;

riscv/insns/fcvt_s_l.h

@@ -1,6 +1,6 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i64_to_f32(RS1));
+WRITE_FRD_F(i64_to_f32(RS1));
 set_fp_exceptions;

riscv/insns/fcvt_s_lu.h

@@ -1,6 +1,6 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui64_to_f32(RS1));
+WRITE_FRD_F(ui64_to_f32(RS1));
 set_fp_exceptions;

riscv/insns/fcvt_s_w.h

@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i32_to_f32((int32_t)RS1));
+WRITE_FRD_F(i32_to_f32((int32_t)RS1));
 set_fp_exceptions;

riscv/insns/fcvt_s_wu.h

@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui32_to_f32((uint32_t)RS1));
+WRITE_FRD_F(ui32_to_f32((uint32_t)RS1));
 set_fp_exceptions;

riscv/insns/fcvt_w_d.h

@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(sext32(f64_to_i32(f64(FRS1), RM, true)));
+WRITE_RD(sext32(f64_to_i32(FRS1_D, RM, true)));
 set_fp_exceptions;

riscv/insns/fcvt_w_h.h

@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(sext32(f16_to_i32(f16(FRS1), RM, true)));
+WRITE_RD(sext32(f16_to_i32(FRS1_H, RM, true)));
 set_fp_exceptions;

riscv/insns/fcvt_w_s.h

@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(sext32(f32_to_i32(f32(FRS1), RM, true)));
+WRITE_RD(sext32(f32_to_i32(FRS1_F, RM, true)));
 set_fp_exceptions;

riscv/insns/fcvt_wu_d.h

@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(sext32(f64_to_ui32(f64(FRS1), RM, true)));
+WRITE_RD(sext32(f64_to_ui32(FRS1_D, RM, true)));
 set_fp_exceptions;

riscv/insns/fcvt_wu_h.h

@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(sext32(f16_to_ui32(f16(FRS1), RM, true)));
+WRITE_RD(sext32(f16_to_ui32(FRS1_H, RM, true)));
 set_fp_exceptions;

riscv/insns/fcvt_wu_s.h

@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(sext32(f32_to_ui32(f32(FRS1), RM, true)));
+WRITE_RD(sext32(f32_to_ui32(FRS1_F, RM, true)));
 set_fp_exceptions;

riscv/insns/fdiv_d.h

@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_div(f64(FRS1), f64(FRS2)));
+WRITE_FRD_D(f64_div(FRS1_D, FRS2_D));
 set_fp_exceptions;

riscv/insns/fdiv_h.h

@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_div(f16(FRS1), f16(FRS2)));
+WRITE_FRD_H(f16_div(FRS1_H, FRS2_H));
 set_fp_exceptions;

riscv/insns/fdiv_s.h

@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_div(f32(FRS1), f32(FRS2)));
+WRITE_FRD_F(f32_div(FRS1_F, FRS2_F));
 set_fp_exceptions;

riscv/insns/feq_d.h

@@ -1,4 +1,4 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-WRITE_RD(f64_eq(f64(FRS1), f64(FRS2)));
+WRITE_RD(f64_eq(FRS1_D, FRS2_D));
 set_fp_exceptions;

riscv/insns/feq_h.h

@@ -1,4 +1,4 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_RD(f16_eq(f16(FRS1), f16(FRS2)));
+WRITE_RD(f16_eq(FRS1_H, FRS2_H));
 set_fp_exceptions;

riscv/insns/feq_s.h

@@ -1,4 +1,4 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-WRITE_RD(f32_eq(f32(FRS1), f32(FRS2)));
+WRITE_RD(f32_eq(FRS1_F, FRS2_F));
 set_fp_exceptions;

riscv/insns/fle_d.h

@@ -1,4 +1,4 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-WRITE_RD(f64_le(f64(FRS1), f64(FRS2)));
+WRITE_RD(f64_le(FRS1_D, FRS2_D));
 set_fp_exceptions;

riscv/insns/fle_h.h

@@ -1,4 +1,4 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_RD(f16_le(f16(FRS1), f16(FRS2)));
+WRITE_RD(f16_le(FRS1_H, FRS2_H));
 set_fp_exceptions;

riscv/insns/fle_s.h

@@ -1,4 +1,4 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-WRITE_RD(f32_le(f32(FRS1), f32(FRS2)));
+WRITE_RD(f32_le(FRS1_F, FRS2_F));
 set_fp_exceptions;

riscv/insns/flt_d.h

@@ -1,4 +1,4 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-WRITE_RD(f64_lt(f64(FRS1), f64(FRS2)));
+WRITE_RD(f64_lt(FRS1_D, FRS2_D));
 set_fp_exceptions;

riscv/insns/flt_h.h

@@ -1,4 +1,4 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_RD(f16_lt(f16(FRS1), f16(FRS2)));
+WRITE_RD(f16_lt(FRS1_H, FRS2_H));
 set_fp_exceptions;

riscv/insns/flt_s.h

@@ -1,4 +1,4 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-WRITE_RD(f32_lt(f32(FRS1), f32(FRS2)));
+WRITE_RD(f32_lt(FRS1_F, FRS2_F));
 set_fp_exceptions;

riscv/insns/fmadd_d.h

@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(FRS3)));
+WRITE_FRD_D(f64_mulAdd(FRS1_D, FRS2_D, FRS3_D));
 set_fp_exceptions;

riscv/insns/fmadd_h.h

@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_mulAdd(f16(FRS1), f16(FRS2), f16(FRS3)));
+WRITE_FRD_H(f16_mulAdd(FRS1_H, FRS2_H, FRS3_H));
 set_fp_exceptions;

riscv/insns/fmadd_s.h

@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(FRS3)));
+WRITE_FRD_F(f32_mulAdd(FRS1_F, FRS2_F, FRS3_F));
 set_fp_exceptions;

riscv/insns/fmax_d.h

@@ -1,9 +1,9 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-bool greater = f64_lt_quiet(f64(FRS2), f64(FRS1)) ||
-               (f64_eq(f64(FRS2), f64(FRS1)) && (f64(FRS2).v & F64_SIGN));
-if (isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v))
-  WRITE_FRD(f64(defaultNaNF64UI));
+bool greater = f64_lt_quiet(FRS2_D, FRS1_D) ||
+              (f64_eq(FRS2_D, FRS1_D) && (FRS2_D.v & F64_SIGN));
+if (isNaNF64UI(FRS1_D.v) && isNaNF64UI(FRS2_D.v))
+  WRITE_FRD_D(f64(defaultNaNF64UI));
 else
-  WRITE_FRD(greater || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
+  WRITE_FRD_D((greater || isNaNF64UI(FRS2_D.v) ? FRS1_D : FRS2_D));
 set_fp_exceptions;

riscv/insns/fmax_h.h

@@ -1,4 +1,4 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_FRD(f16_max(f16(FRS1), f16(FRS2)));
+WRITE_FRD_H(f16_max(FRS1_H, FRS2_H));
 set_fp_exceptions;

riscv/insns/fmax_s.h

@@ -1,9 +1,9 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-bool greater = f32_lt_quiet(f32(FRS2), f32(FRS1)) ||
-               (f32_eq(f32(FRS2), f32(FRS1)) && (f32(FRS2).v & F32_SIGN));
-if (isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v))
-  WRITE_FRD(f32(defaultNaNF32UI));
+bool greater = f32_lt_quiet(FRS2_F, FRS1_F) ||
+               (f32_eq(FRS2_F, FRS1_F) && (FRS2_F.v & F32_SIGN));
+if (isNaNF32UI(FRS1_F.v) && isNaNF32UI(FRS2_F.v))
+  WRITE_FRD_F(f32(defaultNaNF32UI));
 else
-  WRITE_FRD(greater || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
+  WRITE_FRD_F((greater || isNaNF32UI(FRS2_F.v) ? FRS1_F : FRS2_F));
 set_fp_exceptions;

riscv/insns/fmin_d.h

@@ -1,9 +1,9 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-bool less = f64_lt_quiet(f64(FRS1), f64(FRS2)) ||
-            (f64_eq(f64(FRS1), f64(FRS2)) && (f64(FRS1).v & F64_SIGN));
-if (isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v))
-  WRITE_FRD(f64(defaultNaNF64UI));
+bool less = f64_lt_quiet(FRS1_D, FRS2_D) ||
+            (f64_eq(FRS1_D, FRS2_D) && (FRS1_D.v & F64_SIGN));
+if (isNaNF64UI(FRS1_D.v) && isNaNF64UI(FRS2_D.v))
+  WRITE_FRD_D(f64(defaultNaNF64UI));
 else
-  WRITE_FRD(less || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
+  WRITE_FRD_D((less || isNaNF64UI(FRS2_D.v) ? FRS1_D : FRS2_D));
 set_fp_exceptions;

riscv/insns/fmin_h.h

@@ -1,4 +1,4 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_FRD(f16_min(f16(FRS1), f16(FRS2)));
+WRITE_FRD_H(f16_min(FRS1_H, FRS2_H));
 set_fp_exceptions;

riscv/insns/fmin_s.h

@@ -1,9 +1,9 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-bool less = f32_lt_quiet(f32(FRS1), f32(FRS2)) ||
-            (f32_eq(f32(FRS1), f32(FRS2)) && (f32(FRS1).v & F32_SIGN));
-if (isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v))
-  WRITE_FRD(f32(defaultNaNF32UI));
+bool less = f32_lt_quiet(FRS1_F, FRS2_F) ||
+            (f32_eq(FRS1_F, FRS2_F) && (FRS1_F.v & F32_SIGN));
+if (isNaNF32UI(FRS1_F.v) && isNaNF32UI(FRS2_F.v))
+  WRITE_FRD_F(f32(defaultNaNF32UI));
 else
-  WRITE_FRD(less || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
+  WRITE_FRD_F((less || isNaNF32UI(FRS2_F.v) ? FRS1_F : FRS2_F));
 set_fp_exceptions;

riscv/insns/fmsub_d.h

@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(f64(FRS3).v ^ F64_SIGN)));
+WRITE_FRD_D(f64_mulAdd(FRS1_D, FRS2_D, f64(FRS3_D.v ^ F64_SIGN)));
 set_fp_exceptions;

riscv/insns/fmsub_h.h

@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_mulAdd(f16(FRS1), f16(FRS2), f16(f16(FRS3).v ^ F16_SIGN)));
+WRITE_FRD_H(f16_mulAdd(FRS1_H, FRS2_H, f16(FRS3_H.v ^ F16_SIGN)));
 set_fp_exceptions;

riscv/insns/fmsub_s.h

@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(f32(FRS3).v ^ F32_SIGN)));
+WRITE_FRD_F(f32_mulAdd(FRS1_F, FRS2_F, f32(FRS3_F.v ^ F32_SIGN)));
 set_fp_exceptions;

riscv/insns/fmul_d.h

@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_mul(f64(FRS1), f64(FRS2)));
+WRITE_FRD_D(f64_mul(FRS1_D, FRS2_D));
 set_fp_exceptions;

riscv/insns/fmul_h.h

@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_mul(f16(FRS1), f16(FRS2)));
+WRITE_FRD_H(f16_mul(FRS1_H, FRS2_H));
 set_fp_exceptions;

riscv/insns/fmul_s.h

@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mul(f32(FRS1), f32(FRS2)));
+WRITE_FRD_F(f32_mul(FRS1_F, FRS2_F));
 set_fp_exceptions;

riscv/insns/fnmadd_d.h

@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_mulAdd(f64(f64(FRS1).v ^ F64_SIGN), f64(FRS2), f64(f64(FRS3).v ^ F64_SIGN)));
+WRITE_FRD_D(f64_mulAdd(f64(FRS1_D.v ^ F64_SIGN), FRS2_D, f64(FRS3_D.v ^ F64_SIGN)));
 set_fp_exceptions;

riscv/insns/fnmadd_h.h

@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_mulAdd(f16(f16(FRS1).v ^ F16_SIGN), f16(FRS2), f16(f16(FRS3).v ^ F16_SIGN)));
+WRITE_FRD_H(f16_mulAdd(f16(FRS1_H.v ^ F16_SIGN), FRS2_H, f16(FRS3_H.v ^ F16_SIGN)));
 set_fp_exceptions;

riscv/insns/fnmadd_s.h

@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(f32(FRS1).v ^ F32_SIGN), f32(FRS2), f32(f32(FRS3).v ^ F32_SIGN)));
+WRITE_FRD_F(f32_mulAdd(f32(FRS1_F.v ^ F32_SIGN), FRS2_F, f32(FRS3_F.v ^ F32_SIGN)));
 set_fp_exceptions;

riscv/insns/fnmsub_d.h

@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_mulAdd(f64(f64(FRS1).v ^ F64_SIGN), f64(FRS2), f64(FRS3)));
+WRITE_FRD_D(f64_mulAdd(f64(FRS1_D.v ^ F64_SIGN), FRS2_D, FRS3_D));
 set_fp_exceptions;

riscv/insns/fnmsub_h.h

@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_mulAdd(f16(f16(FRS1).v ^ F16_SIGN), f16(FRS2), f16(FRS3)));
+WRITE_FRD_H(f16_mulAdd(f16(FRS1_H.v ^ F16_SIGN), FRS2_H, FRS3_H));
 set_fp_exceptions;

riscv/insns/fnmsub_s.h

@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(f32(FRS1).v ^ F32_SIGN), f32(FRS2), f32(FRS3)));
+WRITE_FRD_F(f32_mulAdd(f32(FRS1_F.v ^ F32_SIGN), FRS2_F, FRS3_F));
 set_fp_exceptions;

riscv/insns/fsgnj_d.h

@@ -1,3 +1,3 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-WRITE_FRD(fsgnj64(FRS1, FRS2, false, false));
+WRITE_FRD_D(fsgnj64(freg(FRS1_D), freg(FRS2_D), false, false));

riscv/insns/fsgnj_h.h

@@ -1,3 +1,3 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_FRD(fsgnj16(FRS1, FRS2, false, false));
+WRITE_FRD_H(fsgnj16(freg(FRS1_H), freg(FRS2_H), false, false));

riscv/insns/fsgnj_s.h

@@ -1,3 +1,3 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-WRITE_FRD(fsgnj32(FRS1, FRS2, false, false));
+WRITE_FRD_F(fsgnj32(freg(FRS1_F), freg(FRS2_F), false, false));

riscv/insns/fsgnjn_d.h

@@ -1,3 +1,3 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-WRITE_FRD(fsgnj64(FRS1, FRS2, true, false));
+WRITE_FRD_D(fsgnj64(freg(FRS1_D), freg(FRS2_D), true, false));

riscv/insns/fsgnjn_h.h

@@ -1,3 +1,3 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_FRD(fsgnj16(FRS1, FRS2, true, false));
+WRITE_FRD_H(fsgnj16(freg(FRS1_H), freg(FRS2_H), true, false));

riscv/insns/fsgnjn_q.h

@@ -1,3 +1,3 @@
 require_extension('Q');
 require_fp;
-WRITE_FRD(fsgnj128(FRS1, FRS2, true, false));
+WRITE_FRD(fsgnj128(FRS1, FRS2, true, false));

riscv/insns/fsgnjn_s.h

@@ -1,3 +1,3 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-WRITE_FRD(fsgnj32(FRS1, FRS2, true, false));
+WRITE_FRD_F(fsgnj32(freg(FRS1_F), freg(FRS2_F), true, false));

riscv/insns/fsgnjx_d.h

@@ -1,3 +1,3 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-WRITE_FRD(fsgnj64(FRS1, FRS2, false, true));
+WRITE_FRD_D(fsgnj64(freg(FRS1_D), freg(FRS2_D), false, true));

riscv/insns/fsgnjx_h.h

@@ -1,3 +1,3 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_FRD(fsgnj16(FRS1, FRS2, false, true));
+WRITE_FRD_H(fsgnj16(freg(FRS1_H), freg(FRS2_H), false, true));

riscv/insns/fsgnjx_s.h

@@ -1,3 +1,3 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-WRITE_FRD(fsgnj32(FRS1, FRS2, false, true));
+WRITE_FRD_F(fsgnj32(freg(FRS1_F), freg(FRS2_F), false, true));

riscv/insns/fsqrt_d.h

@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_sqrt(f64(FRS1)));
+WRITE_FRD_D(f64_sqrt(FRS1_D));
 set_fp_exceptions;

riscv/insns/fsqrt_h.h

@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_sqrt(f16(FRS1)));
+WRITE_FRD_H(f16_sqrt(FRS1_H));
 set_fp_exceptions;

riscv/insns/fsqrt_s.h

@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_sqrt(f32(FRS1)));
+WRITE_FRD_F(f32_sqrt(FRS1_F));
 set_fp_exceptions;

riscv/insns/fsub_d.h

@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_sub(f64(FRS1), f64(FRS2)));
+WRITE_FRD_D(f64_sub(FRS1_D, FRS2_D));
 set_fp_exceptions;

riscv/insns/fsub_h.h

@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_sub(f16(FRS1), f16(FRS2)));
+WRITE_FRD_H(f16_sub(FRS1_H, FRS2_H));
 set_fp_exceptions;

riscv/insns/fsub_s.h

@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_sub(f32(FRS1), f32(FRS2)));
+WRITE_FRD_F(f32_sub(FRS1_F, FRS2_F));
 set_fp_exceptions;

riscv/insns/vfslide1down_vf.h

@@ -23,13 +23,13 @@ if (i != vl - 1) {
 } else {
   switch (P.VU.vsew) {
     case e16:
-      P.VU.elt<float16_t>(rd_num, vl - 1, true) = f16(FRS1);
+      P.VU.elt<float16_t>(rd_num, vl - 1, true) = FRS1_H;
       break;
     case e32:
-      P.VU.elt<float32_t>(rd_num, vl - 1, true) = f32(FRS1);
+      P.VU.elt<float32_t>(rd_num, vl - 1, true) = FRS1_F;
       break;
     case e64:
-      P.VU.elt<float64_t>(rd_num, vl - 1, true) = f64(FRS1);
+      P.VU.elt<float64_t>(rd_num, vl - 1, true) = FRS1_D;
       break;
   }
 }

riscv/insns/vfslide1up_vf.h

@@ -23,13 +23,13 @@ if (i != 0) {
 } else {
   switch (P.VU.vsew) {
     case e16:
-      P.VU.elt<float16_t>(rd_num, 0, true) = f16(FRS1);
+      P.VU.elt<float16_t>(rd_num, 0, true) = FRS1_H;
       break;
     case e32:
-      P.VU.elt<float32_t>(rd_num, 0, true) = f32(FRS1);
+      P.VU.elt<float32_t>(rd_num, 0, true) = FRS1_F;
       break;
     case e64:
-      P.VU.elt<float64_t>(rd_num, 0, true) = f64(FRS1);
+      P.VU.elt<float64_t>(rd_num, 0, true) = FRS1_D;
       break;
   }
 }

riscv/v_ext_macros.h

@@ -1802,7 +1802,7 @@ reg_t index[P.VU.vlmax]; \
     case e16: { \
       float32_t &vd = P.VU.elt<float32_t>(rd_num, i, true); \
       float32_t vs2 = f16_to_f32(P.VU.elt<float16_t>(rs2_num, i)); \
-      float32_t rs1 = f16_to_f32(f16(READ_FREG(rs1_num))); \
+      float32_t rs1 = f16_to_f32(FRS1_H); \
       BODY16; \
       set_fp_exceptions; \
       break; \
@@ -1810,7 +1810,7 @@ reg_t index[P.VU.vlmax]; \
     case e32: { \
       float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \
       float64_t vs2 = f32_to_f64(P.VU.elt<float32_t>(rs2_num, i)); \
-      float64_t rs1 = f32_to_f64(f32(READ_FREG(rs1_num))); \
+      float64_t rs1 = f32_to_f64(FRS1_F); \
       BODY32; \
       set_fp_exceptions; \
       break; \
@@ -1856,7 +1856,7 @@ reg_t index[P.VU.vlmax]; \
     case e16: { \
       float32_t &vd = P.VU.elt<float32_t>(rd_num, i, true); \
       float32_t vs2 = P.VU.elt<float32_t>(rs2_num, i); \
-      float32_t rs1 = f16_to_f32(f16(READ_FREG(rs1_num))); \
+      float32_t rs1 = f16_to_f32(FRS1_H); \
       BODY16; \
       set_fp_exceptions; \
       break; \
@@ -1864,7 +1864,7 @@ reg_t index[P.VU.vlmax]; \
     case e32: { \
       float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \
       float64_t vs2 = P.VU.elt<float64_t>(rs2_num, i); \
-      float64_t rs1 = f32_to_f64(f32(READ_FREG(rs1_num))); \
+      float64_t rs1 = f32_to_f64(FRS1_F); \
       BODY32; \
       set_fp_exceptions; \
       break; \