Use enum to specify the 3 options for masking of intr CSRs

Because using two booleans gives the impression that there are four
possibilities. Since hideleg is itself masked by mideleg, there are
effectively only three choices, so make that explicit via enum.

riscv/csrs.cc

@@ -616,15 +616,14 @@ generic_int_accessor_t::generic_int_accessor_t(state_t* const state,
                                                const reg_t read_mask,
                                                const reg_t ip_write_mask,
                                                const reg_t ie_write_mask,
-                                               const bool mask_mideleg,
-                                               const bool mask_hideleg,
+                                               const mask_mode_t mask_mode,
                                                const int shiftamt):
   state(state),
   read_mask(read_mask),
   ip_write_mask(ip_write_mask),
   ie_write_mask(ie_write_mask),
-  mask_mideleg(mask_mideleg),
-  mask_hideleg(mask_hideleg),
+  mask_mideleg(mask_mode == MIDELEG),
+  mask_hideleg(mask_mode == HIDELEG),
   shiftamt(shiftamt) {
 }
 

riscv/csrs.h

@@ -323,12 +323,13 @@ typedef std::shared_ptr<mie_csr_t> mie_csr_t_p;
 // etc.
 class generic_int_accessor_t {
  public:
+  enum mask_mode_t { NONE, MIDELEG, HIDELEG };
+
   generic_int_accessor_t(state_t* const state,
                          const reg_t read_mask,
                          const reg_t ip_write_mask,
                          const reg_t ie_write_mask,
-                         const bool mask_mideleg,
-                         const bool mask_hideleg,
+                         const mask_mode_t mask_mode,
                          const int shiftamt);
   reg_t ip_read() const noexcept;
   void ip_write(const reg_t val) noexcept;

riscv/processor.cc

@@ -399,8 +399,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
     ~MIP_HS_MASK,  // read_mask
     MIP_SSIP,      // ip_write_mask
     ~MIP_HS_MASK,  // ie_write_mask
-    true,          // mask_mideleg
-    false,         // mask_hideleg
+    generic_int_accessor_t::mask_mode_t::MIDELEG,
     0              // shiftamt
   );
 
@@ -409,8 +408,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
     MIP_HS_MASK,   // read_mask
     MIP_VSSIP,     // ip_write_mask
     MIP_HS_MASK,   // ie_write_mask
-    true,          // mask_mideleg
-    false,         // mask_hideleg
+    generic_int_accessor_t::mask_mode_t::MIDELEG,
     0              // shiftamt
   );
 
@@ -419,8 +417,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
     MIP_VS_MASK,   // read_mask
     MIP_VS_MASK,   // ip_write_mask
     MIP_VS_MASK,   // ie_write_mask
-    false,         // mask_mideleg
-    false,         // mask_hideleg
+    generic_int_accessor_t::mask_mode_t::NONE,
     0              // shiftamt
   );
 
@@ -429,8 +426,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
     MIP_VS_MASK,   // read_mask
     MIP_VSSIP,     // ip_write_mask
     MIP_VS_MASK,   // ie_write_mask
-    false,         // mask_mideleg
-    true,          // mask_hideleg
+    generic_int_accessor_t::mask_mode_t::HIDELEG,
     1              // shiftamt
   );