riscv
/
riscv-isa-sim
mirror of https://github.com/riscv-software-src/riscv-isa-sim.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
Browse Source

Merge pull request #1677 from YenHaoChen/pr-vector-reduction 

vector: Not logging write of reduction instructions when vl = 0
pull/1684/head
Andrew Waterman 2 years ago
committed by GitHub
parent
4611b1f7f9 8ad1b68911
commit
5c3cc772b6
No known key found for this signature in database GPG Key ID: B5690EEEBB952194
1 changed files with 4 additions and 4 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Unified View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 8
      riscv/v_ext_macros.h

8
riscv/v_ext_macros.h
View File

@ -608,7 +608,7 @@ static inline bool is_overlapped_widen(const int astart, int asize,
reg_t rd_num = insn.rd(); \ reg_t rd_num = insn.rd(); \
reg_t rs1_num = insn.rs1(); \ reg_t rs1_num = insn.rs1(); \
reg_t rs2_num = insn.rs2(); \ reg_t rs2_num = insn.rs2(); \
auto &vd_0_des = P.VU.elt<type_sew_t<x>::type>(rd_num, 0, true); \ auto &vd_0_des = P.VU.elt<type_sew_t<x>::type>(rd_num, 0, vl > 0); \
auto vd_0_res = P.VU.elt<type_sew_t<x>::type>(rs1_num, 0); \ auto vd_0_res = P.VU.elt<type_sew_t<x>::type>(rs1_num, 0); \
for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \
VI_LOOP_ELEMENT_SKIP(); \ VI_LOOP_ELEMENT_SKIP(); \
@ -639,7 +639,7 @@ static inline bool is_overlapped_widen(const int astart, int asize,
reg_t rd_num = insn.rd(); \ reg_t rd_num = insn.rd(); \
reg_t rs1_num = insn.rs1(); \ reg_t rs1_num = insn.rs1(); \
reg_t rs2_num = insn.rs2(); \ reg_t rs2_num = insn.rs2(); \
auto &vd_0_des = P.VU.elt<type_usew_t<x>::type>(rd_num, 0, true); \ auto &vd_0_des = P.VU.elt<type_usew_t<x>::type>(rd_num, 0, vl > 0); \
auto vd_0_res = P.VU.elt<type_usew_t<x>::type>(rs1_num, 0); \ auto vd_0_res = P.VU.elt<type_usew_t<x>::type>(rs1_num, 0); \
for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \
VI_LOOP_ELEMENT_SKIP(); \ VI_LOOP_ELEMENT_SKIP(); \
@ -1019,7 +1019,7 @@ static inline bool is_overlapped_widen(const int astart, int asize,
reg_t rd_num = insn.rd(); \ reg_t rd_num = insn.rd(); \
reg_t rs1_num = insn.rs1(); \ reg_t rs1_num = insn.rs1(); \
reg_t rs2_num = insn.rs2(); \ reg_t rs2_num = insn.rs2(); \
auto &vd_0_des = P.VU.elt<type_sew_t<sew2>::type>(rd_num, 0, true); \ auto &vd_0_des = P.VU.elt<type_sew_t<sew2>::type>(rd_num, 0, vl > 0); \
auto vd_0_res = P.VU.elt<type_sew_t<sew2>::type>(rs1_num, 0); \ auto vd_0_res = P.VU.elt<type_sew_t<sew2>::type>(rs1_num, 0); \
for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \
VI_LOOP_ELEMENT_SKIP(); \ VI_LOOP_ELEMENT_SKIP(); \
@ -1047,7 +1047,7 @@ static inline bool is_overlapped_widen(const int astart, int asize,
reg_t rd_num = insn.rd(); \ reg_t rd_num = insn.rd(); \
reg_t rs1_num = insn.rs1(); \ reg_t rs1_num = insn.rs1(); \
reg_t rs2_num = insn.rs2(); \ reg_t rs2_num = insn.rs2(); \
auto &vd_0_des = P.VU.elt<type_usew_t<sew2>::type>(rd_num, 0, true); \ auto &vd_0_des = P.VU.elt<type_usew_t<sew2>::type>(rd_num, 0, vl > 0); \
auto vd_0_res = P.VU.elt<type_usew_t<sew2>::type>(rs1_num, 0); \ auto vd_0_res = P.VU.elt<type_usew_t<sew2>::type>(rs1_num, 0); \
for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \
VI_LOOP_ELEMENT_SKIP(); \ VI_LOOP_ELEMENT_SKIP(); \

Write Preview
Loading…
Cancel
Save