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riscv-isa-sim
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Convert sie/hie/vsie to csr_t family

pull/796/head
Scott Johnson 6 years ago
committed by Andrew Waterman
parent
82bf328e92
commit
5c1d635c6e
3 changed files with 49 additions and 30 deletions
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  1. 25
      riscv/csrs.cc
  2. 14
      riscv/csrs.h
  3. 40
      riscv/processor.cc

25
riscv/csrs.cc
View File

@ -580,12 +580,14 @@ reg_t mie_csr_t::write_mask() const noexcept {
generic_int_accessor_t::generic_int_accessor_t(state_t* const state,
const reg_t read_mask,
const reg_t ip_write_mask,
const reg_t ie_write_mask,
const bool mask_mideleg,
const bool mask_hideleg,
const int shiftamt):
state(state),
read_mask(read_mask),
ip_write_mask(ip_write_mask),
ie_write_mask(ie_write_mask),
mask_mideleg(mask_mideleg),
mask_hideleg(mask_hideleg),
shiftamt(shiftamt) {
@ -600,6 +602,15 @@ void generic_int_accessor_t::ip_write(const reg_t val) noexcept {
state->mip->write_with_mask(mask, val << shiftamt);
}
reg_t generic_int_accessor_t::ie_read() const noexcept {
return (state->mie->read() & deleg_mask() & read_mask) >> shiftamt;
}
void generic_int_accessor_t::ie_write(const reg_t val) noexcept {
const reg_t mask = deleg_mask() & ie_write_mask;
state->mie->write_with_mask(mask, val << shiftamt);
}
reg_t generic_int_accessor_t::deleg_mask() const {
const reg_t hideleg_mask = mask_hideleg ? state->hideleg : (reg_t)~0;
const reg_t mideleg_mask = mask_mideleg ? state->mideleg : (reg_t)~0;
@ -620,3 +631,17 @@ reg_t mip_proxy_csr_t::read() const noexcept {
void mip_proxy_csr_t::write(const reg_t val) noexcept {
accr->ip_write(val);
}
// implement class mie_proxy_csr_t
mie_proxy_csr_t::mie_proxy_csr_t(processor_t* const proc, const reg_t addr, generic_int_accessor_t_p accr):
csr_t(proc, addr),
accr(accr) {
}
reg_t mie_proxy_csr_t::read() const noexcept {
return accr->ie_read();
}
void mie_proxy_csr_t::write(const reg_t val) noexcept {
accr->ie_write(val);
}

14
riscv/csrs.h
View File

@ -304,15 +304,19 @@ class generic_int_accessor_t {
generic_int_accessor_t(state_t* const state,
const reg_t read_mask,
const reg_t ip_write_mask,
const reg_t ie_write_mask,
const bool mask_mideleg,
const bool mask_hideleg,
const int shiftamt);
reg_t ip_read() const noexcept;
void ip_write(const reg_t val) noexcept;
reg_t ie_read() const noexcept;
void ie_write(const reg_t val) noexcept;
private:
state_t* const state;
const reg_t read_mask;
const reg_t ip_write_mask;
const reg_t ie_write_mask;
const bool mask_mideleg;
const bool mask_hideleg;
const int shiftamt;
@ -332,5 +336,15 @@ class mip_proxy_csr_t: public csr_t {
generic_int_accessor_t_p accr;
};
// For all CSRs that are simply (masked & shifted) views into mie
class mie_proxy_csr_t: public csr_t {
public:
mie_proxy_csr_t(processor_t* const proc, const reg_t addr, generic_int_accessor_t_p accr);
virtual reg_t read() const noexcept override;
virtual void write(const reg_t val) noexcept override;
private:
generic_int_accessor_t_p accr;
};
#endif

40
riscv/processor.cc
View File

@ -350,6 +350,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
auto sip_sie_accr = std::make_shared<generic_int_accessor_t>(this,
~MIP_HS_MASK, // read_mask
MIP_SSIP, // ip_write_mask
~MIP_HS_MASK, // ie_write_mask
true, // mask_mideleg
false, // mask_hideleg
0); // shiftamt
@ -357,6 +358,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
auto hip_hie_accr = std::make_shared<generic_int_accessor_t>(this,
MIP_HS_MASK, // read_mask
MIP_VSSIP, // ip_write_mask
MIP_HS_MASK, // ie_write_mask
false, // mask_mideleg
false, // mask_hideleg
0);
@ -364,6 +366,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
auto hvip_accr = std::make_shared<generic_int_accessor_t>(this,
MIP_VS_MASK, // read_mask
MIP_VS_MASK, // ip_write_mask
MIP_VS_MASK, // ie_write_mask
false, // mask_mideleg
false, // mask_hideleg
0); // shiftamt
@ -371,6 +374,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
auto vsip_vsie_accr = std::make_shared<generic_int_accessor_t>(this,
MIP_VS_MASK, // read_mask
MIP_VSSIP, // ip_write_mask
MIP_VSSIP, // ie_write_mask
false, // mask_mideleg
true, // mask_hideleg
1); // shiftamt
@ -382,6 +386,12 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
csrmap[CSR_HIP] = std::make_shared<mip_proxy_csr_t>(proc, CSR_HIP, hip_hie_accr);
csrmap[CSR_HVIP] = std::make_shared<mip_proxy_csr_t>(proc, CSR_HVIP, hvip_accr);
auto nonvirtual_sie = std::make_shared<mie_proxy_csr_t>(proc, CSR_SIE, sip_sie_accr);
auto vsie = std::make_shared<mie_proxy_csr_t>(proc, CSR_VSIE, vsip_vsie_accr);
csrmap[CSR_VSIE] = vsie;
csrmap[CSR_SIE] = std::make_shared<virtualized_csr_t>(proc, nonvirtual_sie, vsie);
csrmap[CSR_HIE] = std::make_shared<mie_proxy_csr_t>(proc, CSR_HIE, hip_hie_accr);
medeleg = 0;
mideleg = 0;
mcounteren = 0;
@ -1014,17 +1024,6 @@ void processor_t::set_csr(int which, reg_t val)
case CSR_MCOUNTEREN:
state.mcounteren = val;
break;
case CSR_SIE: {
reg_t mask;
if (state.v) {
mask = state.hideleg & MIP_VS_MASK;
val = val << 1;
} else {
mask = state.mideleg & ~MIP_HS_MASK;
}
state.mie->write_with_mask(mask, val);
return;
}
case CSR_SATP:
if (!supports_impl(IMPL_MMU))
val = 0;
@ -1070,11 +1069,6 @@ void processor_t::set_csr(int which, reg_t val)
state.hideleg = (state.hideleg & ~mask) | (val & mask);
break;
}
case CSR_HIE: {
reg_t mask = MIP_HS_MASK;
state.mie->write_with_mask(mask, val);
return;
}
case CSR_HCOUNTEREN:
state.hcounteren = val;
break;
@ -1106,11 +1100,6 @@ void processor_t::set_csr(int which, reg_t val)
state.hgatp = val & mask;
break;
}
case CSR_VSIE: {
reg_t mask = state.hideleg & MIP_VS_MASK;
state.mie->write_with_mask(mask, val << 1);
return;
}
case CSR_VSATP:
if (!supports_impl(IMPL_MMU))
val = 0;
@ -1368,13 +1357,6 @@ reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek)
break;
ret(state.mcounteren);
case CSR_MCOUNTINHIBIT: ret(0);
case CSR_SIE: {
if (state.v) {
ret((state.mie->read() & state.hideleg & MIP_VS_MASK) >> 1);
} else {
ret(state.mie->read() & state.mideleg & ~MIP_HS_MASK);
}
}
case CSR_SATP: {
if (state.v) {
if (get_field(state.hstatus, HSTATUS_VTVM))
@ -1413,7 +1395,6 @@ reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek)
case CSR_HSTATUS: ret(state.hstatus);
case CSR_HEDELEG: ret(state.hedeleg);
case CSR_HIDELEG: ret(state.hideleg);
case CSR_HIE: ret(state.mie->read() & MIP_HS_MASK);
case CSR_HCOUNTEREN: ret(state.hcounteren);
case CSR_HGEIE: ret(0);
case CSR_HTVAL: ret(state.htval);
@ -1424,7 +1405,6 @@ reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek)
ret(state.hgatp);
}
case CSR_HGEIP: ret(0);
case CSR_VSIE: ret((state.mie->read() & state.hideleg & MIP_VS_MASK) >> 1);
case CSR_VSATP: ret(state.vsatp);
case CSR_TSELECT: ret(state.tselect);
case CSR_TDATA1:

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