From 5c1a3c40bfe678fa28d44bf3e85abcdede9c0e4d Mon Sep 17 00:00:00 2001 From: Max Chou Date: Fri, 29 May 2026 11:15:45 -0700 Subject: [PATCH] rvp: Fix shift amount masking in PSLL.DWS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use 5-bit mask (0x1F) for shift amount instead of 8-bit field extraction. Spec defines rs2[4:0] as shift amount. Also removes incorrect >= 32 check that zeroed result. Fixed instruction: - PSLL.DWS: P-ext spec Changed: P_FIELD(RS2, 0, 8) with >= 32 check → RS2 & 0x1F Signed-off-by: Max Chou --- riscv/insns/psll_dws.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/riscv/insns/psll_dws.h b/riscv/insns/psll_dws.h index ec71edbf..578814fb 100644 --- a/riscv/insns/psll_dws.h +++ b/riscv/insns/psll_dws.h @@ -1,7 +1,6 @@ require_rv32; P_RD_RS1_DW_LOOP(32, 32, { - uint8_t m = P_FIELD(RS2, 0, 8); + uint8_t m = RS2 & 0x1F; const uint64_t maskN = 0xFFFFFFFFull; - if (m >= 32) p_rd = 0; - else p_rd = (uint32_t)((p_rs1 << m) & maskN); + p_rd = (uint32_t)((p_rs1 << m) & maskN); }) \ No newline at end of file