Force V=1 when going to VS-mode trap handler

Should already be 1.
3 years ago · 5ab7691a49
1 changed files with 1 additions and 0 deletions
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@ -832,6 +832,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
    s = set_field(s, MSTATUS_SPP, state.prv);
    s = set_field(s, MSTATUS_SIE, 0);
    state.sstatus->write(s);
+    set_virt(true);
    set_privilege(PRV_S);
  } else if (state.prv <= PRV_S && bit < max_xlen && ((hsdeleg >> bit) & 1)) {
    // Handle the trap in HS-mode