riscv
/
riscv-isa-sim
mirror of https://github.com/riscv-software-src/riscv-isa-sim.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
Browse Source

rvv: op: change funary op 

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
pull/475/head
Chih-Min Chao 6 years ago
parent
4ece06558c
commit
59aa87bd5d
2 changed files with 56 additions and 50 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 94
      riscv/encoding.h
  2. 12
      spike_main/disasm.cc

94
riscv/encoding.h
View File

@ -1049,51 +1049,51 @@
#define MASK_VFMSAC_VV 0xfc00707f
#define MATCH_VFNMSAC_VV 0xbc001057
#define MASK_VFNMSAC_VV 0xfc00707f
#define MATCH_VFCVT_XU_F_V 0x88001057
#define MATCH_VFCVT_XU_F_V 0x48001057
#define MASK_VFCVT_XU_F_V 0xfc0ff07f
#define MATCH_VFCVT_X_F_V 0x88009057
#define MATCH_VFCVT_X_F_V 0x48009057
#define MASK_VFCVT_X_F_V 0xfc0ff07f
#define MATCH_VFCVT_F_XU_V 0x88011057
#define MATCH_VFCVT_F_XU_V 0x48011057
#define MASK_VFCVT_F_XU_V 0xfc0ff07f
#define MATCH_VFCVT_F_X_V 0x88019057
#define MATCH_VFCVT_F_X_V 0x48019057
#define MASK_VFCVT_F_X_V 0xfc0ff07f
#define MATCH_VFCVT_RTZ_XU_F_V 0x88031057
#define MATCH_VFCVT_RTZ_XU_F_V 0x48031057
#define MASK_VFCVT_RTZ_XU_F_V 0xfc0ff07f
#define MATCH_VFCVT_RTZ_X_F_V 0x88039057
#define MATCH_VFCVT_RTZ_X_F_V 0x48039057
#define MASK_VFCVT_RTZ_X_F_V 0xfc0ff07f
#define MATCH_VFWCVT_XU_F_V 0x88041057
#define MATCH_VFWCVT_XU_F_V 0x48041057
#define MASK_VFWCVT_XU_F_V 0xfc0ff07f
#define MATCH_VFWCVT_X_F_V 0x88049057
#define MATCH_VFWCVT_X_F_V 0x48049057
#define MASK_VFWCVT_X_F_V 0xfc0ff07f
#define MATCH_VFWCVT_F_XU_V 0x88051057
#define MATCH_VFWCVT_F_XU_V 0x48051057
#define MASK_VFWCVT_F_XU_V 0xfc0ff07f
#define MATCH_VFWCVT_F_X_V 0x88059057
#define MATCH_VFWCVT_F_X_V 0x48059057
#define MASK_VFWCVT_F_X_V 0xfc0ff07f
#define MATCH_VFWCVT_F_F_V 0x88061057
#define MATCH_VFWCVT_F_F_V 0x48061057
#define MASK_VFWCVT_F_F_V 0xfc0ff07f
#define MATCH_VFWCVT_RTZ_XU_F_V 0x88071057
#define MATCH_VFWCVT_RTZ_XU_F_V 0x48071057
#define MASK_VFWCVT_RTZ_XU_F_V 0xfc0ff07f
#define MATCH_VFWCVT_RTZ_X_F_V 0x88079057
#define MATCH_VFWCVT_RTZ_X_F_V 0x48079057
#define MASK_VFWCVT_RTZ_X_F_V 0xfc0ff07f
#define MATCH_VFNCVT_XU_F_W 0x88081057
#define MATCH_VFNCVT_XU_F_W 0x48081057
#define MASK_VFNCVT_XU_F_W 0xfc0ff07f
#define MATCH_VFNCVT_X_F_W 0x88089057
#define MATCH_VFNCVT_X_F_W 0x48089057
#define MASK_VFNCVT_X_F_W 0xfc0ff07f
#define MATCH_VFNCVT_F_XU_W 0x88091057
#define MATCH_VFNCVT_F_XU_W 0x48091057
#define MASK_VFNCVT_F_XU_W 0xfc0ff07f
#define MATCH_VFNCVT_F_X_W 0x88099057
#define MATCH_VFNCVT_F_X_W 0x48099057
#define MASK_VFNCVT_F_X_W 0xfc0ff07f
#define MATCH_VFNCVT_F_F_W 0x880a1057
#define MATCH_VFNCVT_F_F_W 0x480a1057
#define MASK_VFNCVT_F_F_W 0xfc0ff07f
#define MATCH_VFNCVT_ROD_F_F_W 0x880a9057
#define MATCH_VFNCVT_ROD_F_F_W 0x480a9057
#define MASK_VFNCVT_ROD_F_F_W 0xfc0ff07f
#define MATCH_VFNCVT_RTZ_XU_F_W 0x880b1057
#define MATCH_VFNCVT_RTZ_XU_F_W 0x480b1057
#define MASK_VFNCVT_RTZ_XU_F_W 0xfc0ff07f
#define MATCH_VFNCVT_RTZ_X_F_W 0x880b9057
#define MATCH_VFNCVT_RTZ_X_F_W 0x480b9057
#define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f
#define MATCH_VFSQRT_V 0x8c001057
#define MATCH_VFSQRT_V 0x4c001057
#define MASK_VFSQRT_V 0xfc0ff07f
#define MATCH_VFCLASS_V 0x8c081057
#define MATCH_VFCLASS_V 0x4c081057
#define MASK_VFCLASS_V 0xfc0ff07f
#define MATCH_VFWADD_VV 0xc0001057
#define MASK_VFWADD_VV 0xfc00707f
@ -1387,6 +1387,20 @@
#define MASK_VASUB_VV 0xfc00707f
#define MATCH_VMV_X_S 0x42002057
#define MASK_VMV_X_S 0xfe0ff07f
#define MATCH_VPOPC_M 0x40082057
#define MASK_VPOPC_M 0xfc0ff07f
#define MATCH_VFIRST_M 0x4008a057
#define MASK_VFIRST_M 0xfc0ff07f
#define MATCH_VMSBF_M 0x5000a057
#define MASK_VMSBF_M 0xfc0ff07f
#define MATCH_VMSOF_M 0x50012057
#define MASK_VMSOF_M 0xfc0ff07f
#define MATCH_VMSIF_M 0x5001a057
#define MASK_VMSIF_M 0xfc0ff07f
#define MATCH_VIOTA_M 0x50082057
#define MASK_VIOTA_M 0xfc0ff07f
#define MATCH_VID_V 0x5008a057
#define MASK_VID_V 0xfdfff07f
#define MATCH_VCOMPRESS_VM 0x5e002057
#define MASK_VCOMPRESS_VM 0xfe00707f
#define MATCH_VMANDNOT_MM 0x60002057
@ -1405,20 +1419,6 @@
#define MASK_VMNOR_MM 0xfc00707f
#define MATCH_VMXNOR_MM 0x7c002057
#define MASK_VMXNOR_MM 0xfc00707f
#define MATCH_VMSBF_M 0x5000a057
#define MASK_VMSBF_M 0xfc0ff07f
#define MATCH_VMSOF_M 0x50012057
#define MASK_VMSOF_M 0xfc0ff07f
#define MATCH_VMSIF_M 0x5001a057
#define MASK_VMSIF_M 0xfc0ff07f
#define MATCH_VIOTA_M 0x50082057
#define MASK_VIOTA_M 0xfc0ff07f
#define MATCH_VID_V 0x5008a057
#define MASK_VID_V 0xfdfff07f
#define MATCH_VPOPC_M 0x40082057
#define MASK_VPOPC_M 0xfc0ff07f
#define MATCH_VFIRST_M 0x4008a057
#define MASK_VFIRST_M 0xfc0ff07f
#define MATCH_VDIVU_VV 0x80002057
#define MASK_VDIVU_VV 0xfc00707f
#define MATCH_VDIV_VV 0x84002057
@ -1479,12 +1479,12 @@
#define MASK_VASUBU_VX 0xfc00707f
#define MATCH_VASUB_VX 0x2c006057
#define MASK_VASUB_VX 0xfc00707f
#define MATCH_VMV_S_X 0x42006057
#define MASK_VMV_S_X 0xfff0707f
#define MATCH_VSLIDE1UP_VX 0x38006057
#define MASK_VSLIDE1UP_VX 0xfc00707f
#define MATCH_VSLIDE1DOWN_VX 0x3c006057
#define MASK_VSLIDE1DOWN_VX 0xfc00707f
#define MATCH_VMV_S_X 0x42006057
#define MASK_VMV_S_X 0xfff0707f
#define MATCH_VDIVU_VX 0x80006057
#define MASK_VDIVU_VX 0xfc00707f
#define MATCH_VDIV_VX 0x84006057
@ -2441,6 +2441,13 @@ DECLARE_INSN(vaadd_vv, MATCH_VAADD_VV, MASK_VAADD_VV)
DECLARE_INSN(vasubu_vv, MATCH_VASUBU_VV, MASK_VASUBU_VV)
DECLARE_INSN(vasub_vv, MATCH_VASUB_VV, MASK_VASUB_VV)
DECLARE_INSN(vmv_x_s, MATCH_VMV_X_S, MASK_VMV_X_S)
DECLARE_INSN(vpopc_m, MATCH_VPOPC_M, MASK_VPOPC_M)
DECLARE_INSN(vfirst_m, MATCH_VFIRST_M, MASK_VFIRST_M)
DECLARE_INSN(vmsbf_m, MATCH_VMSBF_M, MASK_VMSBF_M)
DECLARE_INSN(vmsof_m, MATCH_VMSOF_M, MASK_VMSOF_M)
DECLARE_INSN(vmsif_m, MATCH_VMSIF_M, MASK_VMSIF_M)
DECLARE_INSN(viota_m, MATCH_VIOTA_M, MASK_VIOTA_M)
DECLARE_INSN(vid_v, MATCH_VID_V, MASK_VID_V)
DECLARE_INSN(vcompress_vm, MATCH_VCOMPRESS_VM, MASK_VCOMPRESS_VM)
DECLARE_INSN(vmandnot_mm, MATCH_VMANDNOT_MM, MASK_VMANDNOT_MM)
DECLARE_INSN(vmand_mm, MATCH_VMAND_MM, MASK_VMAND_MM)
@ -2450,13 +2457,6 @@ DECLARE_INSN(vmornot_mm, MATCH_VMORNOT_MM, MASK_VMORNOT_MM)
DECLARE_INSN(vmnand_mm, MATCH_VMNAND_MM, MASK_VMNAND_MM)
DECLARE_INSN(vmnor_mm, MATCH_VMNOR_MM, MASK_VMNOR_MM)
DECLARE_INSN(vmxnor_mm, MATCH_VMXNOR_MM, MASK_VMXNOR_MM)
DECLARE_INSN(vmsbf_m, MATCH_VMSBF_M, MASK_VMSBF_M)
DECLARE_INSN(vmsof_m, MATCH_VMSOF_M, MASK_VMSOF_M)
DECLARE_INSN(vmsif_m, MATCH_VMSIF_M, MASK_VMSIF_M)
DECLARE_INSN(viota_m, MATCH_VIOTA_M, MASK_VIOTA_M)
DECLARE_INSN(vid_v, MATCH_VID_V, MASK_VID_V)
DECLARE_INSN(vpopc_m, MATCH_VPOPC_M, MASK_VPOPC_M)
DECLARE_INSN(vfirst_m, MATCH_VFIRST_M, MASK_VFIRST_M)
DECLARE_INSN(vdivu_vv, MATCH_VDIVU_VV, MASK_VDIVU_VV)
DECLARE_INSN(vdiv_vv, MATCH_VDIV_VV, MASK_VDIV_VV)
DECLARE_INSN(vremu_vv, MATCH_VREMU_VV, MASK_VREMU_VV)
@ -2487,9 +2487,9 @@ DECLARE_INSN(vaaddu_vx, MATCH_VAADDU_VX, MASK_VAADDU_VX)
DECLARE_INSN(vaadd_vx, MATCH_VAADD_VX, MASK_VAADD_VX)
DECLARE_INSN(vasubu_vx, MATCH_VASUBU_VX, MASK_VASUBU_VX)
DECLARE_INSN(vasub_vx, MATCH_VASUB_VX, MASK_VASUB_VX)
DECLARE_INSN(vmv_s_x, MATCH_VMV_S_X, MASK_VMV_S_X)
DECLARE_INSN(vslide1up_vx, MATCH_VSLIDE1UP_VX, MASK_VSLIDE1UP_VX)
DECLARE_INSN(vslide1down_vx, MATCH_VSLIDE1DOWN_VX, MASK_VSLIDE1DOWN_VX)
DECLARE_INSN(vmv_s_x, MATCH_VMV_S_X, MASK_VMV_S_X)
DECLARE_INSN(vdivu_vx, MATCH_VDIVU_VX, MASK_VDIVU_VX)
DECLARE_INSN(vdiv_vx, MATCH_VDIV_VX, MASK_VDIV_VX)
DECLARE_INSN(vremu_vx, MATCH_VREMU_VX, MASK_VREMU_VX)

12
spike_main/disasm.cc
View File

@ -886,21 +886,27 @@ disassembler_t::disassembler_t(int xlen)
DISASM_OPIV_S___INSN(vredmin, 1);
DISASM_OPIV_S___INSN(vredmaxu, 0);
DISASM_OPIV_S___INSN(vredmax, 1);
DISASM_INSN("vmv.x.s", vmv_x_s, 0, {&xrd, &vs2});
DISASM_INSN("vmv.s.x", vmv_s_x, 0, {&vd, &xrs1});
DISASM_OPIV__X__INSN(vslide1up, 1);
DISASM_OPIV__X__INSN(vslide1down,1);
//0b01_0000
//VWXUNARY0
DISASM_INSN("vmv.x.s", vmv_x_s, 0, {&xrd, &vs2});
DISASM_INSN("vpopc.m", vpopc_m, 0, {&xrd, &vs2, &opt, &vm});
//vmuary0
DISASM_INSN("vfirst.m", vfirst_m, 0, {&xrd, &vs2, &opt, &vm});
//VRXUNARY0
DISASM_INSN("vmv.s.x", vmv_s_x, 0, {&vd, &xrs1});
//VMUNARY0
DISASM_INSN("vmsbf.m", vmsbf_m, 0, {&vd, &vs2, &opt, &vm});
DISASM_INSN("vmsof.m", vmsof_m, 0, {&vd, &vs2, &opt, &vm});
DISASM_INSN("vmsif.m", vmsif_m, 0, {&vd, &vs2, &opt, &vm});
DISASM_INSN("viota.m", viota_m, 0, {&vd, &vs2, &opt, &vm});
DISASM_INSN("vid.v", vid_v, 0, {&vd, &opt, &vm});
DISASM_INSN("vid.v", vid_v, 0, {&vd, &opt, &vm});
DISASM_INSN("vcompress.vm", vcompress_vm, 0, {&vd, &vs2, &vs1});
DISASM_OPIV_M___INSN(vmandnot, 1);

Write Preview
Loading…
Cancel
Save