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@ -53,20 +53,6 @@ Spike supports the following RISC-V ISA features: |
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- Zvfbfmin extension, v0.6 |
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- Zvfbfwma extension, v0.6 |
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As a Spike extension, the remainder of the proposed |
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[Bit-Manipulation Extensions](https://github.com/riscv/riscv-bitmanip) |
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is provided under the Spike-custom extension name _Xbitmanip_. |
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These instructions (and, of course, the extension name) are not RISC-V |
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standards. |
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These proposed bit-manipulation extensions can be split into further |
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groups: Zbp, Zbs, Zbe, Zbf, Zbc, Zbm, Zbr, Zbt. Note that Zbc is |
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ratified, but the original proposal contained some extra instructions |
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(64-bit carryless multiplies) which are captured here. |
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To enable these extensions individually, use the Spike-custom |
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extension names _XZbp_, _XZbs_, _XZbc_, and so on. |
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Versioning and APIs |
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------------------- |
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