Update to hopefully final RVC 1.9 encoding

riscv/encoding.h

@@ -531,22 +531,18 @@
 #define MASK_C_SRAI  0xec03
 #define MATCH_C_ANDI 0x8801
 #define MASK_C_ANDI  0xec03
-#define MATCH_C_ADDW 0x8c01
-#define MASK_C_ADDW  0xfc63
-#define MATCH_C_SLL 0x8c21
-#define MASK_C_SLL  0xfc63
-#define MATCH_C_SUBW 0x8c41
-#define MASK_C_SUBW  0xfc63
-#define MATCH_C_SUB 0x8c61
+#define MATCH_C_SUB 0x8c01
 #define MASK_C_SUB  0xfc63
-#define MATCH_C_XOR 0x9c01
+#define MATCH_C_XOR 0x8c21
 #define MASK_C_XOR  0xfc63
-#define MATCH_C_SRL 0x9c21
-#define MASK_C_SRL  0xfc63
-#define MATCH_C_OR 0x9c41
+#define MATCH_C_OR 0x8c41
 #define MASK_C_OR  0xfc63
-#define MATCH_C_AND 0x9c61
+#define MATCH_C_AND 0x8c61
 #define MASK_C_AND  0xfc63
+#define MATCH_C_SUBW 0x9c01
+#define MASK_C_SUBW  0xfc63
+#define MATCH_C_ADDW 0x9c21
+#define MASK_C_ADDW  0xfc63
 #define MATCH_C_J 0xa001
 #define MASK_C_J  0xe003
 #define MATCH_C_BEQZ 0xc001
@@ -837,14 +833,12 @@ DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
 DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
 DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
 DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
-DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
-DECLARE_INSN(c_sll, MATCH_C_SLL, MASK_C_SLL)
-DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
 DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
 DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
-DECLARE_INSN(c_srl, MATCH_C_SRL, MASK_C_SRL)
 DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
 DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
+DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
+DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
 DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
 DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
 DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)

riscv/insns/c_sll.h

@@ -1,2 +0,0 @@
-require_extension('C');
-WRITE_RVC_RS1S(sext_xlen(RVC_RS1S << (RVC_RS2S & (xlen-1))));

riscv/insns/c_srl.h

@@ -1,2 +0,0 @@
-require_extension('C');
-WRITE_RVC_RS1S(sext_xlen(zext_xlen(RVC_RS1S) >> (RVC_RS2S & (xlen-1))));

riscv/riscv.mk.in

@@ -107,10 +107,8 @@ riscv_insn_list = \
 	c_lwsp \
 	c_mv \
 	c_or \
-	c_sll \
 	c_slli \
 	c_srai \
-	c_srl \
 	c_srli \
 	c_sub \
 	c_subw \

spike_main/disasm.cc

@@ -512,8 +512,6 @@ disassembler_t::disassembler_t()
   DISASM_INSN("and", c_and, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_rs2s});
   DISASM_INSN("or", c_or, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_rs2s});
   DISASM_INSN("xor", c_xor, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_rs2s});
-  DISASM_INSN("sll", c_sll, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_rs2s});
-  DISASM_INSN("srl", c_srl, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_rs2s});
   DISASM_INSN("lw", c_lwsp, 0, {&xrd, &rvc_lwsp_address});
   DISASM_INSN("flw", c_flwsp, 0, {&xrd, &rvc_lwsp_address});
   DISASM_INSN("sw", c_swsp, 0, {&rvc_rs2, &rvc_swsp_address});