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Implement new instructions of hypervisor extension

We add new HFENCE, HLV, and HSV instructions for HS-mode which
are defined as part of the RISC-V hypervisor extension.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
pull/493/head
Anup Patel 6 years ago
committed by Anup Patel
parent
commit
564ed97f61
  1. 4
      riscv/insns/hfence_gvma.h
  2. 4
      riscv/insns/hfence_vvma.h
  3. 4
      riscv/insns/hlv_b.h
  4. 4
      riscv/insns/hlv_bu.h
  5. 5
      riscv/insns/hlv_d.h
  6. 4
      riscv/insns/hlv_h.h
  7. 4
      riscv/insns/hlv_hu.h
  8. 4
      riscv/insns/hlv_w.h
  9. 5
      riscv/insns/hlv_wu.h
  10. 4
      riscv/insns/hlvx_hu.h
  11. 4
      riscv/insns/hlvx_wu.h
  12. 4
      riscv/insns/hsv_b.h
  13. 5
      riscv/insns/hsv_d.h
  14. 4
      riscv/insns/hsv_h.h
  15. 4
      riscv/insns/hsv_w.h
  16. 18
      riscv/riscv.mk.in

4
riscv/insns/hfence_gvma.h

@ -0,0 +1,4 @@
require_extension('H');
require_privilege(PRV_S);
require_novirt();
MMU.flush_tlb();

4
riscv/insns/hfence_vvma.h

@ -0,0 +1,4 @@
require_extension('H');
require_privilege(PRV_S);
require_novirt();
MMU.flush_tlb();

4
riscv/insns/hlv_b.h

@ -0,0 +1,4 @@
require_extension('H');
require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
require_novirt();
WRITE_RD(MMU.guest_load_int8(RS1));

4
riscv/insns/hlv_bu.h

@ -0,0 +1,4 @@
require_extension('H');
require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
require_novirt();
WRITE_RD(MMU.guest_load_uint8(RS1));

5
riscv/insns/hlv_d.h

@ -0,0 +1,5 @@
require_extension('H');
require_rv64;
require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
require_novirt();
WRITE_RD(MMU.guest_load_int64(RS1));

4
riscv/insns/hlv_h.h

@ -0,0 +1,4 @@
require_extension('H');
require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
require_novirt();
WRITE_RD(MMU.guest_load_int16(RS1));

4
riscv/insns/hlv_hu.h

@ -0,0 +1,4 @@
require_extension('H');
require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
require_novirt();
WRITE_RD(MMU.guest_load_uint16(RS1));

4
riscv/insns/hlv_w.h

@ -0,0 +1,4 @@
require_extension('H');
require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
require_novirt();
WRITE_RD(MMU.guest_load_int32(RS1));

5
riscv/insns/hlv_wu.h

@ -0,0 +1,5 @@
require_extension('H');
require_rv64;
require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
require_novirt();
WRITE_RD(MMU.guest_load_uint32(RS1));

4
riscv/insns/hlvx_hu.h

@ -0,0 +1,4 @@
require_extension('H');
require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
require_novirt();
WRITE_RD(MMU.guest_load_x_uint16(RS1));

4
riscv/insns/hlvx_wu.h

@ -0,0 +1,4 @@
require_extension('H');
require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
require_novirt();
WRITE_RD(MMU.guest_load_x_uint32(RS1));

4
riscv/insns/hsv_b.h

@ -0,0 +1,4 @@
require_extension('H');
require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
require_novirt();
MMU.guest_store_uint8(RS1, RS2);

5
riscv/insns/hsv_d.h

@ -0,0 +1,5 @@
require_extension('H');
require_rv64;
require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
require_novirt();
MMU.guest_store_uint64(RS1, RS2);

4
riscv/insns/hsv_h.h

@ -0,0 +1,4 @@
require_extension('H');
require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
require_novirt();
MMU.guest_store_uint16(RS1, RS2);

4
riscv/insns/hsv_w.h

@ -0,0 +1,4 @@
require_extension('H');
require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
require_novirt();
MMU.guest_store_uint32(RS1, RS2);

18
riscv/riscv.mk.in

@ -739,6 +739,23 @@ riscv_insn_ext_v = \
$(riscv_insn_ext_v_ctrl) \
$(riscv_insn_ext_v_ldst) \
riscv_insn_ext_h = \
hfence_gvma \
hfence_vvma \
hlv_b \
hlv_bu \
hlv_h \
hlv_hu \
hlvx_hu \
hlv_w \
hlv_wu \
hlvx_wu \
hlv_d \
hsv_b \
hsv_h \
hsv_w \
hsv_d \
riscv_insn_priv = \
csrrc \
csrrci \
@ -765,6 +782,7 @@ riscv_insn_list = \
$(riscv_insn_ext_zfh) \
$(riscv_insn_ext_q) \
$(if $(HAVE_INT128),$(riscv_insn_ext_v),) \
$(riscv_insn_ext_h) \
$(riscv_insn_priv) \
riscv_gen_srcs = \

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