From 51b5702b69083b87575ef8b03592499c3b8d89bd Mon Sep 17 00:00:00 2001 From: Chih-Min Chao Date: Wed, 4 Nov 2020 23:00:49 -0800 Subject: [PATCH] mmu: extract common part of satp and vsatp setting Signed-off-by: Chih-Min Chao --- riscv/processor.cc | 45 ++++++++++++++++++++------------------------- riscv/processor.h | 1 + 2 files changed, 21 insertions(+), 25 deletions(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index 28e16dd5..15801b69 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -805,6 +805,21 @@ int processor_t::paddr_bits() return max_xlen == 64 ? 50 : 34; } +reg_t processor_t::cal_satp(reg_t val) const +{ + reg_t reg_val = 0; + reg_t rv64_ppn_mask = (reg_t(1) << (MAX_PADDR_BITS - PGSHIFT)) - 1; + mmu->flush_tlb(); + if (max_xlen == 32) + reg_val = val & (SATP32_PPN | SATP32_MODE); + + if (max_xlen == 64 && (get_field(val, SATP64_MODE) == SATP_MODE_OFF || + get_field(val, SATP64_MODE) == SATP_MODE_SV39 || + get_field(val, SATP64_MODE) == SATP_MODE_SV48)) + reg_val = val & (SATP64_PPN | SATP64_MODE | rv64_ppn_mask); + + return reg_val; +} void processor_t::set_csr(int which, reg_t val) { #if defined(RISCV_ENABLE_COMMITLOG) @@ -1001,22 +1016,12 @@ void processor_t::set_csr(int which, reg_t val) state.mie = (state.mie & ~mask) | (val & mask); break; } - case CSR_SATP: { - reg_t reg_val = 0; - reg_t rv64_ppn_mask = (reg_t(1) << (MAX_PADDR_BITS - PGSHIFT)) - 1; - mmu->flush_tlb(); - if (max_xlen == 32) - reg_val = val & (SATP32_PPN | SATP32_MODE); - if (max_xlen == 64 && (get_field(val, SATP64_MODE) == SATP_MODE_OFF || - get_field(val, SATP64_MODE) == SATP_MODE_SV39 || - get_field(val, SATP64_MODE) == SATP_MODE_SV48)) - reg_val = val & (SATP64_MODE | (SATP64_PPN & rv64_ppn_mask)); + case CSR_SATP: if (state.v) - state.vsatp = reg_val; + state.vsatp = cal_satp(val); else - state.satp = reg_val; + state.satp = cal_satp(val); break; - } case CSR_SEPC: if (state.v) state.vsepc = val & ~(reg_t)1; @@ -1171,19 +1176,9 @@ void processor_t::set_csr(int which, reg_t val) state.mip = (state.mip & ~mask) | ((val << 1) & mask); break; } - case CSR_VSATP: { - reg_t reg_val = 0; - reg_t rv64_ppn_mask = (reg_t(1) << (MAX_PADDR_BITS - PGSHIFT)) - 1; - mmu->flush_tlb(); - if (max_xlen == 32) - reg_val = val & (SATP32_PPN | SATP32_MODE); - if (max_xlen == 64 && (get_field(val, SATP64_MODE) == SATP_MODE_OFF || - get_field(val, SATP64_MODE) == SATP_MODE_SV39 || - get_field(val, SATP64_MODE) == SATP_MODE_SV48)) - reg_val = val & (SATP64_MODE | (SATP64_PPN & rv64_ppn_mask)); - state.vsatp = reg_val; + case CSR_VSATP: + state.vsatp = cal_satp(val); break; - } case CSR_TSELECT: if (val < state.num_triggers) { state.tselect = val; diff --git a/riscv/processor.h b/riscv/processor.h index 5e75e2fc..74ad526d 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -470,6 +470,7 @@ private: void build_opcode_map(); void register_base_instructions(); insn_func_t decode_insn(insn_t insn); + reg_t cal_satp(reg_t val) const; // Track repeated executions for processor_t::disasm() uint64_t last_pc, last_bits, executions;