Fix multicore debug.

In an older implementation I was thinking of having different entry
points for different harts, but that's no longer true.

Also get rid of a bunch of trailing whitespace.

riscv/processor.cc

@@ -202,7 +202,7 @@ void processor_t::enter_debug_mode(uint8_t cause)
   state.dcsr.prv = state.prv;
   set_privilege(PRV_M);
   state.dpc = state.pc;
-  state.pc = debug_rom_entry();
+  state.pc = DEBUG_ROM_ENTRY;
 }
 
 void processor_t::take_trap(trap_t& t, reg_t epc)
@@ -217,7 +217,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
 
   if (state.dcsr.cause) {
     if (t.cause() == CAUSE_BREAKPOINT) {
-      state.pc = debug_rom_entry();
+      state.pc = DEBUG_ROM_ENTRY;
     } else {
       state.pc = DEBUG_ROM_TVEC;
     }

riscv/processor.h

@@ -194,12 +194,6 @@ public:
   bool slow_path();
   bool halted() { return state.dcsr.cause ? true : false; }
   bool halt_request;
-  // The unique debug rom address that this hart jumps to when entering debug
-  // mode. Rely on the fact that spike hart IDs start at 0 and are consecutive.
-  uint32_t debug_rom_entry() {
-    fprintf(stderr, "Debug_rom_entry called for id %d = %x\n", id, DEBUG_ROM_ENTRY + 4*id);
-    return DEBUG_ROM_ENTRY + 4 * id;
-  }
 
   // Return the index of a trigger that matched, or -1.
   inline int trigger_match(trigger_operation_t operation, reg_t address, reg_t data)