[sim] added atomic memory operations

riscv/execute.h

@@ -245,14 +245,14 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x2:
       {
-        if((insn.bits & 0xfe007fe0) == 0xd0002c20)
+        if((insn.bits & 0xfe007fe0) == 0xd0002020)
         {
-          #include "insns/c_eq_d.h"
+          #include "insns/c_eq_s.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd0002020)
+        if((insn.bits & 0xfe007fe0) == 0xd0002c20)
         {
-          #include "insns/c_eq_s.h"
+          #include "insns/c_eq_d.h"
           break;
         }
         if((insn.bits & 0xfe007fe0) == 0xd0002c60)
@@ -340,6 +340,37 @@ switch((insn.bits >> 0x19) & 0x7f)
     }
     break;
   }
+  case 0x69:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
+    {
+      case 0x2:
+      {
+        #include "insns/l_s.h"
+        break;
+      }
+      case 0x3:
+      {
+        #include "insns/l_d.h"
+        break;
+      }
+      case 0x6:
+      {
+        #include "insns/s_s.h"
+        break;
+      }
+      case 0x7:
+      {
+        #include "insns/s_d.h"
+        break;
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
+    }
+    break;
+  }
   case 0x6a:
   {
     switch((insn.bits >> 0xc) & 0x7)
@@ -808,25 +839,104 @@ switch((insn.bits >> 0x19) & 0x7f)
         #include "insns/sd.h"
         break;
       }
-      case 0x4:
-      {
-        #include "insns/l_s.h"
-        break;
-      }
-      case 0x5:
+      default:
       {
-        #include "insns/l_d.h"
-        break;
+        #include "insns/unimp.h"
       }
-      case 0x6:
+    }
+    break;
+  }
+  case 0x7a:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
+    {
+      case 0x2:
       {
-        #include "insns/s_s.h"
-        break;
+        if((insn.bits & 0xfe007fe0) == 0xf4002040)
+        {
+          #include "insns/amow_and.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xf4002080)
+        {
+          #include "insns/amow_min.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xf4002060)
+        {
+          #include "insns/amow_or.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xf40020a0)
+        {
+          #include "insns/amow_max.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xf40020c0)
+        {
+          #include "insns/amow_minu.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xf4002000)
+        {
+          #include "insns/amow_add.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xf4002020)
+        {
+          #include "insns/amow_swap.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xf40020e0)
+        {
+          #include "insns/amow_maxu.h"
+          break;
+        }
+        #include "insns/unimp.h"
       }
-      case 0x7:
+      case 0x3:
       {
-        #include "insns/s_d.h"
-        break;
+        if((insn.bits & 0xfe007fe0) == 0xf4003000)
+        {
+          #include "insns/amo_add.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xf4003020)
+        {
+          #include "insns/amo_swap.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xf4003060)
+        {
+          #include "insns/amo_or.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xf40030a0)
+        {
+          #include "insns/amo_max.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xf4003080)
+        {
+          #include "insns/amo_min.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xf40030c0)
+        {
+          #include "insns/amo_minu.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xf4003040)
+        {
+          #include "insns/amo_and.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xf40030e0)
+        {
+          #include "insns/amo_maxu.h"
+          break;
+        }
+        #include "insns/unimp.h"
       }
       default:
       {

riscv/insns/amo_add.h

@@ -0,0 +1,4 @@
+require64;
+reg_t v = mmu.load_uint64(RB);
+mmu.store_uint64(RB, RA + v);
+RC = v;

riscv/insns/amo_and.h

@@ -0,0 +1,4 @@
+require64;
+reg_t v = mmu.load_uint64(RB);
+mmu.store_uint64(RB, RA & v);
+RC = v;

riscv/insns/amo_max.h

@@ -0,0 +1,4 @@
+require64;
+sreg_t v = mmu.load_int64(RB);
+mmu.store_uint64(RB, std::max(sreg_t(RA),v));
+RC = v;

riscv/insns/amo_maxu.h

@@ -0,0 +1,4 @@
+require64;
+reg_t v = mmu.load_uint64(RB);
+mmu.store_uint64(RB, std::max(RA,v));
+RC = v;

riscv/insns/amo_min.h

@@ -0,0 +1,4 @@
+require64;
+sreg_t v = mmu.load_int64(RB);
+mmu.store_uint64(RB, std::min(sreg_t(RA),v));
+RC = v;

riscv/insns/amo_minu.h

@@ -0,0 +1,4 @@
+require64;
+reg_t v = mmu.load_uint64(RB);
+mmu.store_uint64(RB, std::min(RA,v));
+RC = v;

riscv/insns/amo_or.h

@@ -0,0 +1,4 @@
+require64;
+reg_t v = mmu.load_uint64(RB);
+mmu.store_uint64(RB, RA | v);
+RC = v;

riscv/insns/amo_swap.h

@@ -0,0 +1,4 @@
+require64;
+reg_t v = mmu.load_uint64(RB);
+mmu.store_uint64(RB, RA);
+RC = v;

riscv/insns/amow_add.h

@@ -0,0 +1,3 @@
+reg_t v = mmu.load_int32(RB);
+mmu.store_uint32(RB, RA + v);
+RC = v;

riscv/insns/amow_and.h

@@ -0,0 +1,3 @@
+reg_t v = mmu.load_int32(RB);
+mmu.store_uint32(RB, RA & v);
+RC = v;

riscv/insns/amow_max.h

@@ -0,0 +1,3 @@
+int32_t v = mmu.load_int32(RB);
+mmu.store_uint32(RB, std::max(int32_t(RA),v));
+RC = v;

riscv/insns/amow_maxu.h

@@ -0,0 +1,3 @@
+uint32_t v = mmu.load_int32(RB);
+mmu.store_uint32(RB, std::max(uint32_t(RA),v));
+RC = v;

riscv/insns/amow_min.h

@@ -0,0 +1,3 @@
+int32_t v = mmu.load_int32(RB);
+mmu.store_uint32(RB, std::min(int32_t(RA),v));
+RC = v;

riscv/insns/amow_minu.h

@@ -0,0 +1,3 @@
+uint32_t v = mmu.load_int32(RB);
+mmu.store_uint32(RB, std::min(uint32_t(RA),v));
+RC = v;

riscv/insns/amow_or.h

@@ -0,0 +1,3 @@
+reg_t v = mmu.load_int32(RB);
+mmu.store_uint32(RB, RA | v);
+RC = v;

riscv/insns/amow_swap.h

@@ -0,0 +1,3 @@
+reg_t v = mmu.load_int32(RB);
+mmu.store_uint32(RB, RA);
+RC = v;