Factor out rounding-mode validation

riscv/decode_macros.h

@@ -146,10 +146,9 @@ do { \
 #define SHAMT (insn.i_imm() & 0x3F)
 #define BRANCH_TARGET (pc + insn.sb_imm())
 #define JUMP_TARGET (pc + insn.uj_imm())
-#define RM ({ int rm = insn.rm(); \
+#define validate_rm(rm) ({ require(rm < 5); rm; })
-              if (rm == 7) rm = STATE.frm->read(); \
+#define VFP_RM validate_rm(STATE.frm->read())
-              if (rm > 4) throw trap_illegal_instruction(insn.bits()); \
+#define RM (insn.rm() == 7 ? VFP_RM : validate_rm(insn.rm()))
-              rm; })
 
 static inline bool is_aligned(const unsigned val, const unsigned pos)
 {

riscv/v_ext_macros.h

@@ -1429,12 +1429,11 @@ VI_VX_ULOOP({ \
 #define VI_VFP_BASE \
   require_fp; \
   require_vector(true); \
-  require(STATE.frm->read() < 0x5); \
   reg_t UNUSED vl = P.VU.vl->read(); \
   reg_t UNUSED rd_num = insn.rd(); \
   reg_t UNUSED rs1_num = insn.rs1(); \
   reg_t UNUSED rs2_num = insn.rs2(); \
-  softfloat_roundingMode = STATE.frm->read()
+  softfloat_roundingMode = VFP_RM
 
 #define VI_VFP_COMMON \
   VI_VFP_BASE; \