[sim] add disable option for vector

config.h.in

@@ -30,6 +30,9 @@
 /* Define if instruction compression is supported */
 #undef RISCV_ENABLE_RVC
 
+/* Define if vector processor is supported */
+#undef RISCV_ENABLE_VEC
+
 /* Define if libopcodes exists */
 #undef RISCV_HAVE_LIBOPCODES
 

configure

@@ -638,6 +638,7 @@ enable_optional_subprojects
 enable_fpu
 enable_64bit
 enable_rvc
+enable_vec
 '
       ac_precious_vars='build_alias
 host_alias
@@ -1273,6 +1274,7 @@ Optional Features:
   --disable-fpu           Disable floating-point
   --disable-64bit         Disable 64-bit mode
   --disable-rvc           Disable instruction compression
+  --disable-vec           Disable vector processor
 
 Some influential environment variables:
   CC          C compiler command
@@ -4058,6 +4060,19 @@ if test "x$enable_rvc" != "xno"; then :
 $as_echo "#define RISCV_ENABLE_RVC /**/" >>confdefs.h
 
 
+fi
+
+# Check whether --enable-vec was given.
+if test "${enable_vec+set}" = set; then :
+  enableval=$enable_vec;
+fi
+
+if test "x$enable_vec" != "xno"; then :
+
+
+$as_echo "#define RISCV_ENABLE_VEC /**/" >>confdefs.h
+
+
 fi
 
 libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a

riscv/processor.cc

@@ -77,6 +77,9 @@ void processor_t::set_sr(uint32_t val)
 #ifndef RISCV_ENABLE_RVC
   sr &= ~SR_EC;
 #endif
+#ifndef RISCV_ENABLE_VEC
+  sr &= ~SR_EV;
+#endif
 
   xprlen = ((sr & SR_S) ? (sr & SR_SX) : (sr & SR_UX)) ? 64 : 32;
 }

riscv/riscv.ac

@@ -13,6 +13,11 @@ AS_IF([test "x$enable_rvc" != "xno"], [
   AC_DEFINE([RISCV_ENABLE_RVC],,[Define if instruction compression is supported])
 ])
 
+AC_ARG_ENABLE([vec], AS_HELP_STRING([--disable-vec], [Disable vector processor]))
+AS_IF([test "x$enable_vec" != "xno"], [
+  AC_DEFINE([RISCV_ENABLE_VEC],,[Define if vector processor is supported])
+])
+
 libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a
 AC_CHECK_FILES([$libopc],[have_libopcodes="yes"],[have_libopcodes="no"])