From 49d1d2a80294e921ad2a34536e78973234e2c7b9 Mon Sep 17 00:00:00 2001
From: DymShanks <166487860+DymShanks@users.noreply.github.com>
Date: Sat, 24 Jan 2026 19:37:01 +0000
Subject: [PATCH] Fix: Enforce virtual_instruction trap for VU-mode indirect
 CSR access

---
 riscv/csrs.cc | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/riscv/csrs.cc b/riscv/csrs.cc
index 249c76d5..6424e037 100644
--- a/riscv/csrs.cc
+++ b/riscv/csrs.cc
@@ -1852,6 +1852,10 @@ sscsrind_reg_csr_t::sscsrind_reg_csr_t(processor_t* const proc, const reg_t addr
 }
 
 void sscsrind_reg_csr_t::verify_permissions(insn_t insn, bool write) const {
+  if (state->v && state->prv == PRV_U) {
+     throw trap_virtual_instruction(insn.bits());
+  }
+
   if (proc->extension_enabled(EXT_SMSTATEEN)) {
     if ((state->prv < PRV_M) && !(state->mstateen[0]->read() & MSTATEEN0_CSRIND))
       throw trap_illegal_instruction(insn.bits());