fixes to correctly simulate the vector unit

13 years ago · 4944ab3c02
3 changed files with 5 additions and 1 deletions
--- a/2
+++ b/2
@ -1,7 +1,7 @@
 ==========================================================================
 RISC-V ISA Simulator
 ==========================================================================
-# Author  : Andrew Waterman
+# Author  : Andrew Waterman, Yunsup Lee
 # Date    : June 19, 2011
 # Version : (under version control)

--- a/riscv/decode.h
+++ b/riscv/decode.h
@ -152,6 +152,8 @@ public:
  }
  write_port_t<T> write_port(size_t i)
  {
+    if (zero_reg)
+      const_cast<T&>(data[0]) = 0;
    return write_port_t<T>(data[i]);
  }
  const T& operator [] (size_t i) const
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@ -299,6 +299,8 @@ reg_t processor_t::get_pcr(int which)
      return pcr_k1;
    case PCR_VECBANK:
      return vecbanks;
+    case PCR_VECCFG:
+      return nfpr_use << 18 | nxpr_use << 12 | vl;
    case PCR_TOHOST:
      return tohost;
    case PCR_FROMHOST: