diff --git a/riscv/insns/vwmulsu_vv.h b/riscv/insns/vwmulsu_vv.h index 5f84721f..ec373771 100644 --- a/riscv/insns/vwmulsu_vv.h +++ b/riscv/insns/vwmulsu_vv.h @@ -2,15 +2,5 @@ VI_CHECK_DSS(true); VI_VV_LOOP_WIDEN ({ - switch(P.VU.vsew) { - case e8: - P.VU.elt(rd_num, i, true) = (int16_t)(int8_t)vs2 * (int16_t)(uint8_t)vs1; - break; - case e16: - P.VU.elt(rd_num, i, true) = (int32_t)(int16_t)vs2 * (int32_t)(uint16_t)vs1; - break; - default: - P.VU.elt(rd_num, i, true) = (int64_t)(int32_t)vs2 * (int64_t)(uint32_t)vs1; - break; - } + VI_WIDE_OP_AND_ASSIGN_MIX(vs2, vs1, 0, *, +, uint, int, uint) }) diff --git a/riscv/insns/vwmulsu_vx.h b/riscv/insns/vwmulsu_vx.h index 68d6d276..d58ecce0 100644 --- a/riscv/insns/vwmulsu_vx.h +++ b/riscv/insns/vwmulsu_vx.h @@ -2,15 +2,5 @@ VI_CHECK_DSS(false); VI_VX_LOOP_WIDEN ({ - switch(P.VU.vsew) { - case e8: - P.VU.elt(rd_num, i, true) = (int16_t)(int8_t)vs2 * (int16_t)(uint8_t)rs1; - break; - case e16: - P.VU.elt(rd_num, i, true) = (int32_t)(int16_t)vs2 * (int32_t)(uint16_t)rs1; - break; - default: - P.VU.elt(rd_num, i, true) = (int64_t)(int32_t)vs2 * (int64_t)(uint32_t)rs1; - break; - } + VI_WIDE_OP_AND_ASSIGN_MIX(vs2, rs1, 0, *, +, uint, int, uint) })