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Simplify vwmulsu_vv and vwmulsu_vx (#861)
Leverage macro VI_WIDE_OP_AND_ASSIGN_MIX
pull/880/head
Yueh-Ting (eop) Chen
4 years ago
committed by
GitHub
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with
2 additions and
22 deletions
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riscv/insns/vwmulsu_vv.h
-
riscv/insns/vwmulsu_vx.h
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@ -2,15 +2,5 @@ |
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VI_CHECK_DSS(true); |
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VI_VV_LOOP_WIDEN |
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({ |
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switch(P.VU.vsew) { |
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case e8: |
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P.VU.elt<uint16_t>(rd_num, i, true) = (int16_t)(int8_t)vs2 * (int16_t)(uint8_t)vs1; |
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break; |
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case e16: |
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P.VU.elt<uint32_t>(rd_num, i, true) = (int32_t)(int16_t)vs2 * (int32_t)(uint16_t)vs1; |
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break; |
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default: |
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P.VU.elt<uint64_t>(rd_num, i, true) = (int64_t)(int32_t)vs2 * (int64_t)(uint32_t)vs1; |
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break; |
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} |
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VI_WIDE_OP_AND_ASSIGN_MIX(vs2, vs1, 0, *, +, uint, int, uint) |
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}) |
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@ -2,15 +2,5 @@ |
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VI_CHECK_DSS(false); |
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VI_VX_LOOP_WIDEN |
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({ |
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switch(P.VU.vsew) { |
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case e8: |
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P.VU.elt<uint16_t>(rd_num, i, true) = (int16_t)(int8_t)vs2 * (int16_t)(uint8_t)rs1; |
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break; |
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case e16: |
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P.VU.elt<uint32_t>(rd_num, i, true) = (int32_t)(int16_t)vs2 * (int32_t)(uint16_t)rs1; |
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break; |
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default: |
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P.VU.elt<uint64_t>(rd_num, i, true) = (int64_t)(int32_t)vs2 * (int64_t)(uint32_t)rs1; |
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break; |
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} |
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VI_WIDE_OP_AND_ASSIGN_MIX(vs2, rs1, 0, *, +, uint, int, uint) |
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}) |
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