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riscv-isa-sim
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rvv: replace vn suffic by 'w' 

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
pull/366/head
Chih-Min Chao 7 years ago
parent
8d50b2ff66
commit
47c0eb64c8
15 changed files with 78 additions and 74 deletions
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  1. 72
      riscv/encoding.h
  2. 0
      riscv/insns/vnclip_wi.h
  3. 0
      riscv/insns/vnclip_wv.h
  4. 0
      riscv/insns/vnclip_wx.h
  5. 0
      riscv/insns/vnclipu_wi.h
  6. 0
      riscv/insns/vnclipu_wv.h
  7. 0
      riscv/insns/vnclipu_wx.h
  8. 0
      riscv/insns/vnsra_wi.h
  9. 0
      riscv/insns/vnsra_wv.h
  10. 0
      riscv/insns/vnsra_wx.h
  11. 0
      riscv/insns/vnsrl_wi.h
  12. 0
      riscv/insns/vnsrl_wv.h
  13. 0
      riscv/insns/vnsrl_wx.h
  14. 24
      riscv/riscv.mk.in
  15. 56
      spike_main/disasm.cc

72
riscv/encoding.h
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@ -1120,14 +1120,14 @@
#define MASK_VSSRL_VX 0xfc00707f
#define MATCH_VSSRA_VX 0xac004057
#define MASK_VSSRA_VX 0xfc00707f
#define MATCH_VNSRL_VX 0xb0004057
#define MASK_VNSRL_VX 0xfc00707f
#define MATCH_VNSRA_VX 0xb4004057
#define MASK_VNSRA_VX 0xfc00707f
#define MATCH_VNCLIPU_VX 0xb8004057
#define MASK_VNCLIPU_VX 0xfc00707f
#define MATCH_VNCLIP_VX 0xbc004057
#define MASK_VNCLIP_VX 0xfc00707f
#define MATCH_VNSRL_WX 0xb0004057
#define MASK_VNSRL_WX 0xfc00707f
#define MATCH_VNSRA_WX 0xb4004057
#define MASK_VNSRA_WX 0xfc00707f
#define MATCH_VNCLIPU_WX 0xb8004057
#define MASK_VNCLIPU_WX 0xfc00707f
#define MATCH_VNCLIP_WX 0xbc004057
#define MASK_VNCLIP_WX 0xfc00707f
#define MATCH_VQMACCU_VX 0xf0004057
#define MASK_VQMACCU_VX 0xfc00707f
#define MATCH_VQMACC_VX 0xf4004057
@ -1200,14 +1200,14 @@
#define MASK_VSSRL_VV 0xfc00707f
#define MATCH_VSSRA_VV 0xac000057
#define MASK_VSSRA_VV 0xfc00707f
#define MATCH_VNSRL_VV 0xb0000057
#define MASK_VNSRL_VV 0xfc00707f
#define MATCH_VNSRA_VV 0xb4000057
#define MASK_VNSRA_VV 0xfc00707f
#define MATCH_VNCLIPU_VV 0xb8000057
#define MASK_VNCLIPU_VV 0xfc00707f
#define MATCH_VNCLIP_VV 0xbc000057
#define MASK_VNCLIP_VV 0xfc00707f
#define MATCH_VNSRL_WV 0xb0000057
#define MASK_VNSRL_WV 0xfc00707f
#define MATCH_VNSRA_WV 0xb4000057
#define MASK_VNSRA_WV 0xfc00707f
#define MATCH_VNCLIPU_WV 0xb8000057
#define MASK_VNCLIPU_WV 0xfc00707f
#define MATCH_VNCLIP_WV 0xbc000057
#define MASK_VNCLIP_WV 0xfc00707f
#define MATCH_VWREDSUMU_VS 0xc0000057
#define MASK_VWREDSUMU_VS 0xfc00707f
#define MATCH_VWREDSUM_VS 0xc4000057
@ -1272,14 +1272,14 @@
#define MASK_VSSRL_VI 0xfc00707f
#define MATCH_VSSRA_VI 0xac003057
#define MASK_VSSRA_VI 0xfc00707f
#define MATCH_VNSRL_VI 0xb0003057
#define MASK_VNSRL_VI 0xfc00707f
#define MATCH_VNSRA_VI 0xb4003057
#define MASK_VNSRA_VI 0xfc00707f
#define MATCH_VNCLIPU_VI 0xb8003057
#define MASK_VNCLIPU_VI 0xfc00707f
#define MATCH_VNCLIP_VI 0xbc003057
#define MASK_VNCLIP_VI 0xfc00707f
#define MATCH_VNSRL_WI 0xb0003057
#define MASK_VNSRL_WI 0xfc00707f
#define MATCH_VNSRA_WI 0xb4003057
#define MASK_VNSRA_WI 0xfc00707f
#define MATCH_VNCLIPU_WI 0xb8003057
#define MASK_VNCLIPU_WI 0xfc00707f
#define MATCH_VNCLIP_WI 0xbc003057
#define MASK_VNCLIP_WI 0xfc00707f
#define MATCH_VREDSUM_VS 0x2057
#define MASK_VREDSUM_VS 0xfc00707f
#define MATCH_VREDAND_VS 0x4002057
@ -2231,10 +2231,10 @@ DECLARE_INSN(vsrl_vx, MATCH_VSRL_VX, MASK_VSRL_VX)
DECLARE_INSN(vsra_vx, MATCH_VSRA_VX, MASK_VSRA_VX)
DECLARE_INSN(vssrl_vx, MATCH_VSSRL_VX, MASK_VSSRL_VX)
DECLARE_INSN(vssra_vx, MATCH_VSSRA_VX, MASK_VSSRA_VX)
DECLARE_INSN(vnsrl_vx, MATCH_VNSRL_VX, MASK_VNSRL_VX)
DECLARE_INSN(vnsra_vx, MATCH_VNSRA_VX, MASK_VNSRA_VX)
DECLARE_INSN(vnclipu_vx, MATCH_VNCLIPU_VX, MASK_VNCLIPU_VX)
DECLARE_INSN(vnclip_vx, MATCH_VNCLIP_VX, MASK_VNCLIP_VX)
DECLARE_INSN(vnsrl_wx, MATCH_VNSRL_WX, MASK_VNSRL_WX)
DECLARE_INSN(vnsra_wx, MATCH_VNSRA_WX, MASK_VNSRA_WX)
DECLARE_INSN(vnclipu_wx, MATCH_VNCLIPU_WX, MASK_VNCLIPU_WX)
DECLARE_INSN(vnclip_wx, MATCH_VNCLIP_WX, MASK_VNCLIP_WX)
DECLARE_INSN(vqmaccu_vx, MATCH_VQMACCU_VX, MASK_VQMACCU_VX)
DECLARE_INSN(vqmacc_vx, MATCH_VQMACC_VX, MASK_VQMACC_VX)
DECLARE_INSN(vqmaccus_vx, MATCH_VQMACCUS_VX, MASK_VQMACCUS_VX)
@ -2271,10 +2271,10 @@ DECLARE_INSN(vsrl_vv, MATCH_VSRL_VV, MASK_VSRL_VV)
DECLARE_INSN(vsra_vv, MATCH_VSRA_VV, MASK_VSRA_VV)
DECLARE_INSN(vssrl_vv, MATCH_VSSRL_VV, MASK_VSSRL_VV)
DECLARE_INSN(vssra_vv, MATCH_VSSRA_VV, MASK_VSSRA_VV)
DECLARE_INSN(vnsrl_vv, MATCH_VNSRL_VV, MASK_VNSRL_VV)
DECLARE_INSN(vnsra_vv, MATCH_VNSRA_VV, MASK_VNSRA_VV)
DECLARE_INSN(vnclipu_vv, MATCH_VNCLIPU_VV, MASK_VNCLIPU_VV)
DECLARE_INSN(vnclip_vv, MATCH_VNCLIP_VV, MASK_VNCLIP_VV)
DECLARE_INSN(vnsrl_wv, MATCH_VNSRL_WV, MASK_VNSRL_WV)
DECLARE_INSN(vnsra_wv, MATCH_VNSRA_WV, MASK_VNSRA_WV)
DECLARE_INSN(vnclipu_wv, MATCH_VNCLIPU_WV, MASK_VNCLIPU_WV)
DECLARE_INSN(vnclip_wv, MATCH_VNCLIP_WV, MASK_VNCLIP_WV)
DECLARE_INSN(vwredsumu_vs, MATCH_VWREDSUMU_VS, MASK_VWREDSUMU_VS)
DECLARE_INSN(vwredsum_vs, MATCH_VWREDSUM_VS, MASK_VWREDSUM_VS)
DECLARE_INSN(vdotu_vv, MATCH_VDOTU_VV, MASK_VDOTU_VV)
@ -2307,10 +2307,10 @@ DECLARE_INSN(vsrl_vi, MATCH_VSRL_VI, MASK_VSRL_VI)
DECLARE_INSN(vsra_vi, MATCH_VSRA_VI, MASK_VSRA_VI)
DECLARE_INSN(vssrl_vi, MATCH_VSSRL_VI, MASK_VSSRL_VI)
DECLARE_INSN(vssra_vi, MATCH_VSSRA_VI, MASK_VSSRA_VI)
DECLARE_INSN(vnsrl_vi, MATCH_VNSRL_VI, MASK_VNSRL_VI)
DECLARE_INSN(vnsra_vi, MATCH_VNSRA_VI, MASK_VNSRA_VI)
DECLARE_INSN(vnclipu_vi, MATCH_VNCLIPU_VI, MASK_VNCLIPU_VI)
DECLARE_INSN(vnclip_vi, MATCH_VNCLIP_VI, MASK_VNCLIP_VI)
DECLARE_INSN(vnsrl_wi, MATCH_VNSRL_WI, MASK_VNSRL_WI)
DECLARE_INSN(vnsra_wi, MATCH_VNSRA_WI, MASK_VNSRA_WI)
DECLARE_INSN(vnclipu_wi, MATCH_VNCLIPU_WI, MASK_VNCLIPU_WI)
DECLARE_INSN(vnclip_wi, MATCH_VNCLIP_WI, MASK_VNCLIP_WI)
DECLARE_INSN(vredsum_vs, MATCH_VREDSUM_VS, MASK_VREDSUM_VS)
DECLARE_INSN(vredand_vs, MATCH_VREDAND_VS, MASK_VREDAND_VS)
DECLARE_INSN(vredor_vs, MATCH_VREDOR_VS, MASK_VREDOR_VS)

0
riscv/insns/vnclip_vi.h → riscv/insns/vnclip_wi.h
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0
riscv/insns/vnclip_vv.h → riscv/insns/vnclip_wv.h
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0
riscv/insns/vnclip_vx.h → riscv/insns/vnclip_wx.h
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0
riscv/insns/vnclipu_vi.h → riscv/insns/vnclipu_wi.h
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0
riscv/insns/vnclipu_vv.h → riscv/insns/vnclipu_wv.h
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0
riscv/insns/vnclipu_vx.h → riscv/insns/vnclipu_wx.h
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0
riscv/insns/vnsra_vi.h → riscv/insns/vnsra_wi.h
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0
riscv/insns/vnsra_vv.h → riscv/insns/vnsra_wv.h
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0
riscv/insns/vnsra_vx.h → riscv/insns/vnsra_wx.h
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0
riscv/insns/vnsrl_vi.h → riscv/insns/vnsrl_wi.h
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0
riscv/insns/vnsrl_vv.h → riscv/insns/vnsrl_wv.h
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0
riscv/insns/vnsrl_vx.h → riscv/insns/vnsrl_wx.h
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24
riscv/riscv.mk.in
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@ -382,22 +382,22 @@ riscv_insn_ext_v_alu_int = \
vmv_x_s \
vmxnor_mm \
vmxor_mm \
vnclip_vi \
vnclip_vv \
vnclip_vx \
vnclipu_vi \
vnclipu_vv \
vnclipu_vx \
vnclip_wi \
vnclip_wv \
vnclip_wx \
vnclipu_wi \
vnclipu_wv \
vnclipu_wx \
vnmsac_vv \
vnmsac_vx \
vnmsub_vv \
vnmsub_vx \
vnsra_vi \
vnsra_vv \
vnsra_vx \
vnsrl_vi \
vnsrl_vv \
vnsrl_vx \
vnsra_wi \
vnsra_wv \
vnsra_wx \
vnsrl_wi \
vnsrl_wv \
vnsrl_wx \
vor_vi \
vor_vv \
vor_vx \

56
spike_main/disasm.cc
View File

@ -805,17 +805,21 @@ disassembler_t::disassembler_t(int xlen)
DISASM_INSN("vl1r.v", vl1r_v, 0, {&vd, &v_address});
DISASM_INSN("vs1r.v", vs1r_v, 0, {&vs3, &v_address});
#define DISASM_OPIV_VXI_INSN(name, sign) \
add_insn(new disasm_insn_t(#name ".vv", match_##name##_vv, mask_##name##_vv, \
#define DISASM_OPIV_VXI_INSN(name, sign, suf) \
add_insn(new disasm_insn_t(#name "." #suf "v", \
match_##name##_##suf##v, mask_##name##_##suf##v, \
{&vd, &vs2, &vs1, &opt, &vm})); \
add_insn(new disasm_insn_t(#name ".vx", match_##name##_vx, mask_##name##_vx, \
add_insn(new disasm_insn_t(#name "." #suf "x", \
match_##name##_##suf##x, mask_##name##_##suf##x, \
{&vd, &vs2, &xrs1, &opt, &vm})); \
if (sign) \
add_insn(new disasm_insn_t(#name ".vi", match_##name##_vi, mask_##name##_vi, \
add_insn(new disasm_insn_t(#name "." #suf "i", \
match_##name##_##suf##i, mask_##name##_##suf##i, \
{&vd, &vs2, &v_simm5, &opt, &vm})); \
else \
add_insn(new disasm_insn_t(#name ".vi", match_##name##_vi, mask_##name##_vi, \
{&vd, &vs2, &zimm5, &opt, &vm}));
add_insn(new disasm_insn_t(#name "." #suf "i", \
match_##name##_##suf##i, mask_##name##_##suf##i, \
{&vd, &vs2, &zimm5, &opt, &vm}));
#define DISASM_OPIV_VX__INSN(name, sign) \
add_insn(new disasm_insn_t(#name ".vv", match_##name##_vv, mask_##name##_vv, \
@ -869,17 +873,17 @@ disassembler_t::disassembler_t(int xlen)
//OPFVV/OPFVF
//0b00_0000
DISASM_OPIV_VXI_INSN(vadd, 1);
DISASM_OPIV_VXI_INSN(vadd, 1, v);
DISASM_OPIV_VX__INSN(vsub, 1);
DISASM_OPIV__XI_INSN(vrsub, 1);
DISASM_OPIV_VX__INSN(vminu, 0);
DISASM_OPIV_VX__INSN(vmin, 1);
DISASM_OPIV_VX__INSN(vmaxu, 1);
DISASM_OPIV_VX__INSN(vmax, 0);
DISASM_OPIV_VXI_INSN(vand, 1);
DISASM_OPIV_VXI_INSN(vor, 1);
DISASM_OPIV_VXI_INSN(vxor, 1);
DISASM_OPIV_VXI_INSN(vrgather, 0);
DISASM_OPIV_VXI_INSN(vand, 1, v);
DISASM_OPIV_VXI_INSN(vor, 1, v);
DISASM_OPIV_VXI_INSN(vxor, 1, v);
DISASM_OPIV_VXI_INSN(vrgather, 0, v);
DISASM_OPIV__XI_INSN(vslideup, 1);
DISASM_OPIV__XI_INSN(vslidedown,1);
@ -892,34 +896,34 @@ disassembler_t::disassembler_t(int xlen)
DISASM_INSN("vmv.v.i", vmv_v_i, 0, {&vd, &v_simm5});
DISASM_INSN("vmv.v.v", vmv_v_v, 0, {&vd, &vs1});
DISASM_INSN("vmv.v.x", vmv_v_x, 0, {&vd, &xrs1});
DISASM_OPIV_VXI_INSN(vmseq, 1);
DISASM_OPIV_VXI_INSN(vmsne, 1);
DISASM_OPIV_VXI_INSN(vmseq, 1, v);
DISASM_OPIV_VXI_INSN(vmsne, 1, v);
DISASM_OPIV_VX__INSN(vmsltu, 0);
DISASM_OPIV_VX__INSN(vmslt, 1);
DISASM_OPIV_VXI_INSN(vmsleu, 0);
DISASM_OPIV_VXI_INSN(vmsle, 1);
DISASM_OPIV_VXI_INSN(vmsleu, 0, v);
DISASM_OPIV_VXI_INSN(vmsle, 1, v);
DISASM_OPIV__XI_INSN(vmsgtu, 0);
DISASM_OPIV__XI_INSN(vmsgt, 1);
//0b10_0000
DISASM_OPIV_VXI_INSN(vsaddu, 0);
DISASM_OPIV_VXI_INSN(vsadd, 1);
DISASM_OPIV_VXI_INSN(vsaddu, 0, v);
DISASM_OPIV_VXI_INSN(vsadd, 1, v);
DISASM_OPIV_VX__INSN(vssubu, 0);
DISASM_OPIV_VX__INSN(vssub, 1);
DISASM_OPIV_VXI_INSN(vsll, 1);
DISASM_OPIV_VXI_INSN(vsll, 1, v);
DISASM_OPIV_VX__INSN(vaaddu, 0);
DISASM_OPIV_VX__INSN(vaadd, 0);
DISASM_OPIV_VX__INSN(vasubu, 0);
DISASM_OPIV_VX__INSN(vasub, 0);
DISASM_OPIV_VX__INSN(vsmul, 1);
DISASM_OPIV_VXI_INSN(vsrl, 0);
DISASM_OPIV_VXI_INSN(vsra, 0);
DISASM_OPIV_VXI_INSN(vssrl, 0);
DISASM_OPIV_VXI_INSN(vssra, 0);
DISASM_OPIV_VXI_INSN(vnsrl, 0);
DISASM_OPIV_VXI_INSN(vnsra, 0);
DISASM_OPIV_VXI_INSN(vnclipu, 0);
DISASM_OPIV_VXI_INSN(vnclip, 1);
DISASM_OPIV_VXI_INSN(vsrl, 0, v);
DISASM_OPIV_VXI_INSN(vsra, 0, v);
DISASM_OPIV_VXI_INSN(vssrl, 0, v);
DISASM_OPIV_VXI_INSN(vssra, 0, v);
DISASM_OPIV_VXI_INSN(vnsrl, 0, w);
DISASM_OPIV_VXI_INSN(vnsra, 0, w);
DISASM_OPIV_VXI_INSN(vnclipu, 0, w);
DISASM_OPIV_VXI_INSN(vnclip, 1, w);
//0b11_0000
DISASM_OPIV_S___INSN(vwredsumu, 0);

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