rvp: Fix multiply-accumulate result extraction shift amount

Corrects shift amount for extracting bits [47:16] from 48-bit
multiply-accumulate products. Implementation used 32-bit shift
but spec requires 16-bit shift to extract high portion.

Fixed instructions:
- MHACC.H0: P-ext spec
- MHACC.H1: P-ext spec
- MHACCSU.H0: P-ext spec
- MHACCSU.H1: P-ext spec

Changed: mres >> 32  →  mres >> 16

Signed-off-by: Max Chou <max.chou@sifive.com>

riscv/insns/mhacc_h0.h

@@ -1,4 +1,4 @@
 require_extension('P');
 require_rv32;
 sreg_t mres = sext32(RS1) * sext32(P_FIELD(RS2, 0, 16));
-WRITE_RD(RD + (mres >> 32));
+WRITE_RD(RD + (mres >> 16));

riscv/insns/mhacc_h1.h

@@ -1,4 +1,4 @@
 require_extension('P');
 require_rv32;
 sreg_t mres = sext32(RS1) * sext32(P_FIELD(RS2, 1, 16));
-WRITE_RD(RD + (mres >> 32));
+WRITE_RD(RD + (mres >> 16));

riscv/insns/mhaccsu_h0.h

@@ -1,4 +1,4 @@
 require_extension('P');
 require_rv32;
 sreg_t mres = sext32(RS1) * (uint32_t)P_FIELD(RS2, 0, 16);
-WRITE_RD(RD + (mres >> 32));
+WRITE_RD(RD + (mres >> 16));

riscv/insns/mhaccsu_h1.h

@@ -1,4 +1,4 @@
 require_extension('P');
 require_rv32;
 sreg_t mres = sext32(RS1) * (uint32_t)P_FIELD(RS2, 1, 16);
-WRITE_RD(RD + (mres >> 32));
+WRITE_RD(RD + (mres >> 16));