[sim, xcc] bthread threading model exposed; insn encoding cleaned up

riscv/execute.h

@@ -377,7 +377,7 @@ switch((insn.bits >> 0x19) & 0x7f)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe007fff) == 0xd4000000)
+        if((insn.bits & 0xfe0fffe0) == 0xd4000000)
         {
           #include "insns/mff_s.h"
           break;
@@ -386,7 +386,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x1:
       {
-        if((insn.bits & 0xfe007fff) == 0xd4001000)
+        if((insn.bits & 0xfe0fffe0) == 0xd4001000)
         {
           #include "insns/mff_d.h"
           break;
@@ -395,7 +395,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x4:
       {
-        if((insn.bits & 0xfe007fff) == 0xd4004000)
+        if((insn.bits & 0xfe0fffe0) == 0xd4004000)
         {
           #include "insns/mtf_s.h"
           break;
@@ -404,7 +404,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x5:
       {
-        if((insn.bits & 0xfe007fff) == 0xd4005000)
+        if((insn.bits & 0xfe0fffe0) == 0xd4005000)
         {
           #include "insns/mtf_d.h"
           break;
@@ -979,18 +979,18 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x2:
       {
-        if((insn.bits & 0xfe0fffe0) == 0xf6002000)
+        if((insn.bits & 0xfff07fe0) == 0xf6002000)
         {
-          #include "insns/rdhwr.h"
+          #include "insns/mfcr.h"
           break;
         }
         #include "insns/unimp.h"
       }
       case 0x3:
       {
-        if((insn.bits & 0xffffffff) == 0xf6003000)
+        if((insn.bits & 0xfe007fff) == 0xf6003000)
         {
-          #include "insns/sync.h"
+          #include "insns/mtcr.h"
           break;
         }
         #include "insns/unimp.h"
@@ -999,7 +999,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       {
         if((insn.bits & 0xffffffff) == 0xf6004000)
         {
-          #include "insns/syscall.h"
+          #include "insns/sync.h"
           break;
         }
         #include "insns/unimp.h"
@@ -1007,6 +1007,15 @@ switch((insn.bits >> 0x19) & 0x7f)
       case 0x5:
       {
         if((insn.bits & 0xffffffff) == 0xf6005000)
+        {
+          #include "insns/syscall.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x6:
+      {
+        if((insn.bits & 0xffffffff) == 0xf6006000)
         {
           #include "insns/break.h"
           break;
@@ -1026,7 +1035,7 @@ switch((insn.bits >> 0x19) & 0x7f)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe0fffff) == 0xfc000000)
+        if((insn.bits & 0xffffffe0) == 0xfc000000)
         {
           #include "insns/ei.h"
           break;
@@ -1035,7 +1044,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x1:
       {
-        if((insn.bits & 0xfe0fffff) == 0xfc001000)
+        if((insn.bits & 0xffffffe0) == 0xfc001000)
         {
           #include "insns/di.h"
           break;
@@ -1053,7 +1062,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x4:
       {
-        if((insn.bits & 0xfe007fff) == 0xfc004000)
+        if((insn.bits & 0xfff07fe0) == 0xfc004000)
         {
           #include "insns/mfpcr.h"
           break;
@@ -1063,30 +1072,12 @@ switch((insn.bits >> 0x19) & 0x7f)
       case 0x5:
       {
         if((insn.bits & 0xfe007fff) == 0xfc005000)
-        {
-          #include "insns/mwfpcr.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x6:
-      {
-        if((insn.bits & 0xfe007fff) == 0xfc006000)
         {
           #include "insns/mtpcr.h"
           break;
         }
         #include "insns/unimp.h"
       }
-      case 0x7:
-      {
-        if((insn.bits & 0xfe007fff) == 0xfc007000)
-        {
-          #include "insns/mwtpcr.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
       default:
       {
         #include "insns/unimp.h"

riscv/insns/di.h

@@ -1,4 +1,4 @@
 require_supervisor;
 uint32_t temp = sr;
 set_sr(sr & ~SR_ET);
-RA = temp;
+RC = temp;

riscv/insns/ei.h

@@ -1,4 +1,4 @@
 require_supervisor;
 uint32_t temp = sr;
 set_sr(sr | SR_ET);
-RA = temp;
+RC = temp;

riscv/insns/mfcr.h

@@ -0,0 +1,17 @@
+reg_t val;
+
+switch(insn.rtype.rb)
+{
+  case 1:
+    val = 32; // synci_step
+    break;
+
+  case 29:
+    val = tid;
+    break;
+
+  default:
+    val = -1;
+}
+
+RC = gprlen == 64 ? val : sext32(val);

riscv/insns/mff_d.h

@@ -1,3 +1,3 @@
 require64;
 require_fp;
-RA = FRB;
+RC = FRA;

riscv/insns/mff_s.h

@@ -1,2 +1,2 @@
 require_fp;
-RA = sext32(FRB);
+RC = sext32(FRA);

riscv/insns/mfpcr.h

@@ -29,4 +29,4 @@ switch(insn.rtype.rb)
     val = -1;
 }
 
-RA = gprlen == 64 ? val : sext32(val);
+RC = gprlen == 64 ? val : sext32(val);

riscv/insns/mtcr.h

@@ -0,0 +1,8 @@
+reg_t val = gprlen == 64 ? RA : sext32(RA);
+
+switch(insn.rtype.rb)
+{
+  case 29:
+    tid = val;
+    break;
+}

riscv/insns/mtf_d.h

@@ -1,3 +1,3 @@
 require64;
 require_fp;
-FRA = RB;
+FRC = RA;

riscv/insns/mtf_s.h

@@ -1,2 +1,2 @@
 require_fp;
-FRA = sext32(RB);
+FRC = sext32(RA);

riscv/processor.cc

@@ -18,6 +18,7 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
   ebase = 0;
   epc = 0;
   badvaddr = 0;
+  tid = 0;
   set_sr(SR_S | (support_64bit ? SR_KX : 0));
   set_fsr(0);
 

riscv/processor.h

@@ -21,13 +21,20 @@ private:
   // architected state
   reg_t R[NGPR];
   freg_t FR[NFPR];
+
+  // privileged control registers
   reg_t pc;
   reg_t epc;
   reg_t badvaddr;
   reg_t ebase;
   uint32_t id;
   uint32_t sr;
+
+  // unprivileged control registers
+  uint32_t tid;
   uint32_t fsr;
+
+  // 32-bit or 64-bit mode (redundant with sr)
   int gprlen;
 
   // shared memory