From 4557eef7005d648953ec00210c84cc234e1dd1eb Mon Sep 17 00:00:00 2001
From: "Yueh-Ting (eop) Chen" <eop.chen@sifive.com>
Date: Wed, 26 Jan 2022 06:05:20 +0800
Subject: [PATCH] Add more assertion for fcvt (#910)

---
 riscv/decode.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/riscv/decode.h b/riscv/decode.h
index 8b372c2f..c2912e45 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -2392,6 +2392,7 @@ reg_t index[P.VU.vlmax]; \
 
 #define VI_VFP_CVT_INT_TO_FP(BODY16, BODY32, BODY64, sign) \
   VI_CHECK_SSS(false); \
+  VI_VFP_COMMON \
   switch(P.VU.vsew) { \
     case e16: \
       { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(16, 16, sign), \
@@ -2415,6 +2416,7 @@ reg_t index[P.VU.vlmax]; \
 
 #define VI_VFP_CVT_FP_TO_INT(BODY16, BODY32, BODY64, sign) \
   VI_CHECK_SSS(false); \
+  VI_VFP_COMMON \
   switch(P.VU.vsew) { \
     case e16: \
       { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(16, 16, sign), \