From 4484d17bd22721b8b91c6b5c916f08ec1c4dd53d Mon Sep 17 00:00:00 2001
From: YenHaoChen <howard25336284@gmail.com>
Date: Mon, 26 Feb 2024 16:11:45 +0800
Subject: [PATCH] AIA: Add read-only 0 mvien CSR (minimal required
 implementation)

---
 riscv/csr_init.cc | 7 +++++++
 riscv/processor.h | 2 ++
 2 files changed, 9 insertions(+)

diff --git a/riscv/csr_init.cc b/riscv/csr_init.cc
index 0992b4c4..26f5b67d 100644
--- a/riscv/csr_init.cc
+++ b/riscv/csr_init.cc
@@ -475,7 +475,14 @@ void state_t::csr_init(processor_t* const proc, reg_t max_isa)
   const reg_t srmcfg_mask = SRMCFG_MCID | SRMCFG_RCID;
   add_const_ext_csr(EXT_SSQOSID, CSR_SRMCFG, std::make_shared<srmcfg_csr_t>(proc, CSR_SRMCFG, srmcfg_mask, 0));
 
+  mvien = std::make_shared<const_csr_t>(proc, CSR_MVIEN, 0);
   if (proc->extension_enabled_const(EXT_SMAIA)) {
     add_csr(CSR_MTOPI, std::make_shared<mtopi_csr_t>(proc, CSR_MTOPI));
+    if (xlen == 32) {
+      add_supervisor_csr(CSR_MVIEN, std::make_shared<rv32_low_csr_t>(proc, CSR_MVIEN, mvien));
+      add_supervisor_csr(CSR_MVIENH, std::make_shared<rv32_high_csr_t>(proc, CSR_MVIENH, mvien));
+    } else {
+      add_supervisor_csr(CSR_MVIEN, mvien);
+    }
   }
 }
diff --git a/riscv/processor.h b/riscv/processor.h
index 994e92d7..d6e69eab 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -174,6 +174,8 @@ struct state_t
 
   csr_t_p ssp;
 
+  csr_t_p mvien;
+
   bool serialized; // whether timer CSRs are in a well-defined state
 
   // When true, execute a single instruction and then enter debug mode.  This