Provide vxsat when P extension is implemented

Signed-off-by: Andrew Waterman <andrew@sifive.com>

riscv/csr_init.cc

@@ -342,6 +342,10 @@ void state_t::csr_init(processor_t* const proc, reg_t max_isa)
   assert(FSR_AEXC_SHIFT == 0);  // composite_csr_t assumes fflags begins at bit 0
   add_csr(CSR_FCSR, std::make_shared<composite_csr_t>(proc, CSR_FCSR, frm, fflags, FSR_RD_SHIFT));
 
+  if (proc->extension_enabled('P') || proc->any_vector_extensions()) {
+    add_csr(CSR_VXSAT, vxsat = std::make_shared<vxsat_csr_t>(proc, CSR_VXSAT));
+  }
+
   add_ext_csr(EXT_ZKR, CSR_SEED, std::make_shared<seed_csr_t>(proc, CSR_SEED));
 
   add_csr(CSR_MARCHID, std::make_shared<const_csr_t>(proc, CSR_MARCHID, 5));

riscv/csrs.cc

@@ -1752,12 +1752,13 @@ vxsat_csr_t::vxsat_csr_t(processor_t* const proc, const reg_t addr):
 }
 
 void vxsat_csr_t::verify_permissions(insn_t insn, bool write) const {
-  require(proc->any_vector_extensions() && STATE.sstatus->enabled(SSTATUS_VS));
+  require(!proc->any_vector_extensions() || STATE.sstatus->enabled(SSTATUS_VS));
   masked_csr_t::verify_permissions(insn, write);
 }
 
 bool vxsat_csr_t::unlogged_write(const reg_t val) noexcept {
-  STATE.sstatus->dirty(SSTATUS_VS);
+  if (proc->any_vector_extensions())
+    STATE.sstatus->dirty(SSTATUS_VS);
   return masked_csr_t::unlogged_write(val);
 }
 

riscv/processor.h

@@ -171,6 +171,8 @@ struct state_t
   float_csr_t_p fflags;
   float_csr_t_p frm;
 
+  csr_t_p vxsat;
+
   csr_t_p menvcfg;
   csr_t_p senvcfg;
   csr_t_p henvcfg;
@@ -315,7 +317,7 @@ public:
     return ~(reg_t)(ialign == 16 ? 0 : 2);
   }
   void set_vxsat() {
-    VU.vxsat->write(1);
+    state.vxsat->write(1);
   }
   reg_t throw_instruction_address_misaligned(reg_t pc);
   reg_t legalize_privilege(reg_t);

riscv/vector_unit.cc

@@ -14,14 +14,13 @@ void vectorUnit_t::vectorUnit_t::reset()
   memset(reg_file, 0, NVPR * vlenb);
 
   auto state = p->get_state();
-  state->add_csr(CSR_VXSAT, vxsat = std::make_shared<vxsat_csr_t>(p, CSR_VXSAT));
   state->add_csr(CSR_VSTART, vstart = std::make_shared<vector_csr_t>(p, CSR_VSTART, /*mask*/ VLEN - 1));
   state->add_csr(CSR_VXRM, vxrm = std::make_shared<vector_csr_t>(p, CSR_VXRM, /*mask*/ 0x3ul));
   state->add_csr(CSR_VL, vl = std::make_shared<vector_csr_t>(p, CSR_VL, /*mask*/ 0));
   state->add_csr(CSR_VTYPE, vtype = std::make_shared<vector_csr_t>(p, CSR_VTYPE, /*mask*/ 0));
   state->add_csr(CSR_VLENB, std::make_shared<vector_csr_t>(p, CSR_VLENB, /*mask*/ 0, /*init*/ vlenb));
   assert(VCSR_VXSAT_SHIFT == 0);  // composite_csr_t assumes vxsat begins at bit 0
-  state->add_csr(CSR_VCSR, std::make_shared<composite_csr_t>(p, CSR_VCSR, vxrm, vxsat, VCSR_VXRM_SHIFT));
+  state->add_csr(CSR_VCSR, std::make_shared<composite_csr_t>(p, CSR_VCSR, vxrm, state->vxsat, VCSR_VXRM_SHIFT));
 
   vtype->write_raw(0);
   set_vl(0, 0, 0, -1); // default to illegal configuration

riscv/vector_unit.h

@@ -92,7 +92,6 @@ public:
   int setvl_count = 0;
   reg_t vlmax = 0;
   reg_t vlenb = 0;
-  csr_t_p vxsat = 0;
   vector_csr_t_p vxrm = 0, vstart = 0, vl = 0, vtype = 0;
   reg_t vma = 0, vta = 0;
   reg_t vsew = 0;