add blocksz parameter to specify the cache block size for CBO operations

riscv/mmu.h

@@ -389,12 +389,18 @@ public:
     return target_big_endian? target_endian<T>::to_be(n) : target_endian<T>::to_le(n);
   }
 
+  void set_cache_blocksz(uint64_t size)
+  {
+    blocksz = size;
+  }
+
 private:
   simif_t* sim;
   processor_t* proc;
   memtracer_list_t tracer;
   reg_t load_reservation_address;
   uint16_t fetch_temp;
+  uint64_t blocksz;
 
   // implement an instruction cache for simulator performance
   icache_entry_t icache[ICACHE_ENTRIES];

spike_main/spike.cc

@@ -72,6 +72,7 @@ static void help(int exit_code = 1)
   fprintf(stderr, "  --dm-no-abstract-csr  Debug module won't support abstract to authenticate\n");
   fprintf(stderr, "  --dm-no-halt-groups   Debug module won't support halt groups\n");
   fprintf(stderr, "  --dm-no-impebreak     Debug module won't support implicit ebreak in program buffer\n");
+  fprintf(stderr, "  --blocksz=<size>     Cache block size (B) for CMO operations(powers of 2) [default 16]\n");
 
   exit(exit_code);
 }
@@ -241,6 +242,7 @@ int main(int argc, char** argv)
   uint16_t rbb_port = 0;
   bool use_rbb = false;
   unsigned dmi_rti = 0;
+  reg_t blocksz = 64;
   debug_module_config_t dm_config = {
     .progbufsize = 2,
     .max_sba_data_width = 0,
@@ -376,6 +378,13 @@ int main(int argc, char** argv)
         exit(-1);
      }
   });
+  parser.option(0, "blocksz", 1, [&](const char* s){
+    blocksz = strtoull(s, 0, 0);
+    if (((blocksz & (blocksz - 1))) != 0) {
+      fprintf(stderr, "--blocksz should be power of 2\n");
+      exit(-1);
+    }
+  });
 
   auto argv1 = parser.parse(argv);
   std::vector<std::string> htif_args(argv1, (const char*const*)argv + argc);
@@ -464,6 +473,7 @@ int main(int argc, char** argv)
     if (dc) s.get_core(i)->get_mmu()->register_memtracer(&*dc);
     for (auto e : extensions)
       s.get_core(i)->register_extension(e());
+    s.get_core(i)->get_mmu()->set_cache_blocksz(blocksz);
   }
 
   s.set_debug(debug);