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@ -343,7 +343,8 @@ bool plic_t::load(reg_t addr, size_t len, uint8_t* bytes) |
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return false; |
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} |
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if (PRIORITY_BASE <= addr && addr < PENDING_BASE) { |
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static_assert(PRIORITY_BASE == 0); |
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if (/* PRIORITY_BASE <= addr && */ addr < PENDING_BASE) { |
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ret = priority_read(addr, &val); |
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} else if (PENDING_BASE <= addr && addr < ENABLE_BASE) { |
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ret = pending_read(addr - PENDING_BASE, &val); |
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@ -384,7 +385,8 @@ bool plic_t::store(reg_t addr, size_t len, const uint8_t* bytes) |
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write_little_endian_reg(&val, addr, len, bytes); |
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if (PRIORITY_BASE <= addr && addr < ENABLE_BASE) { |
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static_assert(PRIORITY_BASE == 0); |
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if (/* PRIORITY_BASE <= addr && */ addr < ENABLE_BASE) { |
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ret = priority_write(addr, val); |
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} else if (ENABLE_BASE <= addr && addr < CONTEXT_BASE) { |
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uint32_t cntx = (addr - ENABLE_BASE) / ENABLE_PER_HART; |
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