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riscv-isa-sim
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rvv: support new mstatus.vs field defined in v0.8 

mstatus.vs is similiar to mstatus.fs and used to control the state of
vector unit.

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
pull/366/head
Chih-Min Chao 7 years ago
parent
b812e15a8c
commit
4051af5ce6
4 changed files with 38 additions and 15 deletions
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  1. 2
      README.md
  2. 24
      riscv/decode.h
  3. 2
      riscv/encoding.h
  4. 25
      riscv/processor.cc

2
README.md
View File

@ -18,7 +18,7 @@ Spike supports the following RISC-V ISA features:
- D extension, v2.2
- Q extension, v2.2
- C extension, v2.0
- V extension, v0.8-draft-20191004, w/ Zvlsseg, w/o Zvamo/Zvediv, (_requires a 64-bit host_)
- V extension, v0.8-draft-20191118, w/ Zvlsseg, w/o Zvamo/Zvediv, (_requires a 64-bit host_)
- Conformance to both RVWMO and RVTSO (Spike is sequentially consistent)
- Machine, Supervisor, and User modes, v1.11
- Debug v0.14

24
riscv/decode.h
View File

@ -34,6 +34,12 @@ const int NCSR = 4096;
#define X_RA 1
#define X_SP 2
#define FSR_VXRM_SHIFT 9
#define FSR_VXRM (0x3 << FSR_VXRM_SHIFT)
#define FSR_VXSAT_SHIFT 8
#define FSR_VXSAT (0x1 << FSR_VXSAT_SHIFT)
#define FP_RD_NE 0
#define FP_RD_0 1
#define FP_RD_DN 2
@ -184,6 +190,7 @@ private:
#define FRS3 READ_FREG(insn.rs3())
#define dirty_fp_state (STATE.mstatus |= MSTATUS_FS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
#define dirty_ext_state (STATE.mstatus |= MSTATUS_XS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
#define dirty_vs_state (STATE.mstatus |= MSTATUS_VS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
#define DO_WRITE_FREG(reg, value) (STATE.FPR.write(reg, value), dirty_fp_state)
#define WRITE_FRD(value) WRITE_FREG(insn.rd(), value)
@ -206,9 +213,20 @@ private:
#define require_fp require((STATE.mstatus & MSTATUS_FS) != 0)
#define require_accelerator require((STATE.mstatus & MSTATUS_XS) != 0)
#define require_vector_vs do { } while (0) // TODO MSTATUS_VS
#define require_vector do { require_vector_vs; require_extension('V'); require(!P.VU.vill); } while (0)
#define require_vector_for_vsetvl do { require_vector_vs; require_extension('V'); } while (0)
#define require_vector_vs require((STATE.mstatus & MSTATUS_VS) != 0);
#define require_vector \
do { \
require_vector_vs; \
require_extension('V'); \
require(!P.VU.vill); \
dirty_vs_state; \
} while (0);
#define require_vector_for_vsetvl \
do { \
require_vector_vs; \
require_extension('V'); \
dirty_vs_state; \
} while (0);
#define set_fp_exceptions ({ if (softfloat_exceptionFlags) { \
dirty_fp_state; \

2
riscv/encoding.h
View File

@ -22,6 +22,7 @@
#define MSTATUS_TVM 0x00100000
#define MSTATUS_TW 0x00200000
#define MSTATUS_TSR 0x00400000
#define MSTATUS_VS 0x01800000
#define MSTATUS32_SD 0x80000000
#define MSTATUS_UXL 0x0000000300000000
#define MSTATUS_SXL 0x0000000C00000000
@ -36,6 +37,7 @@
#define SSTATUS_XS 0x00018000
#define SSTATUS_SUM 0x00040000
#define SSTATUS_MXR 0x00080000
#define SSTATUS_VS 0x01800000
#define SSTATUS32_SD 0x80000000
#define SSTATUS_UXL 0x0000000300000000
#define SSTATUS64_SD 0x8000000000000000

25
riscv/processor.cc
View File

@ -532,6 +532,10 @@ void processor_t::set_csr(int which, reg_t val)
dirty_fp_state;
state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
if (supports_extension('V')) {
VU.vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
VU.vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT;
}
break;
case CSR_MSTATUS: {
if ((val ^ state.mstatus) &
@ -540,6 +544,7 @@ void processor_t::set_csr(int which, reg_t val)
bool has_fs = supports_extension('S') || supports_extension('F')
|| supports_extension('V');
bool has_vs = supports_extension('V');
reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
| MSTATUS_MPRV
@ -547,6 +552,7 @@ void processor_t::set_csr(int which, reg_t val)
| MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
| MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL |
(has_fs ? MSTATUS_FS : 0) |
(has_vs ? MSTATUS_VS : 0) |
(ext ? MSTATUS_XS : 0);
reg_t requested_mpp = legalize_privilege(get_field(val, MSTATUS_MPP));
@ -558,6 +564,7 @@ void processor_t::set_csr(int which, reg_t val)
bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
dirty |= (state.mstatus & MSTATUS_VS) == MSTATUS_VS;
if (max_xlen == 32)
state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
else
@ -616,7 +623,8 @@ void processor_t::set_csr(int which, reg_t val)
break;
case CSR_SSTATUS: {
reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
| SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
| SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR
| (supports_extension('V') ? SSTATUS_VS : 0);
return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
}
case CSR_SIP: {
@ -724,12 +732,15 @@ void processor_t::set_csr(int which, reg_t val)
state.dscratch1 = val;
break;
case CSR_VSTART:
dirty_vs_state;
VU.vstart = val;
break;
case CSR_VXSAT:
dirty_fp_state;
VU.vxsat = val;
break;
case CSR_VXRM:
dirty_fp_state;
VU.vxrm = val;
break;
}
@ -909,33 +920,25 @@ reg_t processor_t::get_csr(int which)
return state.dscratch1;
case CSR_VSTART:
require_vector_vs;
if (!supports_extension('V'))
break;
return VU.vstart;
case CSR_VXSAT:
require_vector_vs;
require_fp;
if (!supports_extension('V'))
break;
return VU.vxsat;
case CSR_VXRM:
require_vector_vs;
require_fp;
if (!supports_extension('V'))
break;
return VU.vxrm;
case CSR_VL:
require_vector_vs;
if (!supports_extension('V'))
break;
return VU.vl;
case CSR_VTYPE:
require_vector_vs;
if (!supports_extension('V'))
break;
return VU.vtype;
case CSR_VLENB:
require_vector_vs;
if (!supports_extension('V'))
break;
return VU.vlenb;
}
throw trap_illegal_instruction(0);

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