work towards rvc 1.8

riscv/decode.h

@@ -77,6 +77,7 @@ public:
   uint64_t csr() { return x(20, 12); }
 
   int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); }
+  int64_t rvc_zimm() { return x(2, 5) + (x(12, 1) << 5); }
   int64_t rvc_addi4spn_imm() { return (x(6, 1) << 2) + (x(5, 1) << 3) + (x(11, 2) << 4) + (x(7, 4) << 6); }
   int64_t rvc_addi16sp_imm() { return (x(6, 1) << 4) + (x(5, 1) << 5) + (x(2, 3) << 6) + (xs(12, 1) << 9); }
   int64_t rvc_lwsp_imm() { return (x(4, 3) << 2) + (x(12, 1) << 5) + (x(2, 2) << 6); }
@@ -84,6 +85,7 @@ public:
   int64_t rvc_swsp_imm() { return (x(9, 4) << 2) + (x(7, 2) << 6); }
   int64_t rvc_sdsp_imm() { return (x(10, 3) << 3) + (x(7, 3) << 6); }
   int64_t rvc_lw_imm() { return (x(6, 1) << 2) + (x(10, 3) << 3) + (x(5, 1) << 6); }
+  int64_t rvc_lb_imm() { return (x(12, 1) + (x(5, 2) << 1) + (x(10, 2) << 3)); }
   int64_t rvc_ld_imm() { return (x(10, 3) << 3) + (x(5, 2) << 6); }
   int64_t rvc_j_imm() { return (x(3, 4) << 1) + (x(2, 1) << 5) + (xs(7, 6) << 6); }
   int64_t rvc_b_imm() { return (x(3, 4) << 1) + (x(2, 1) << 5) + (xs(10, 3) << 6); }
@@ -142,6 +144,7 @@ private:
 #endif
 
 // RVC macros
+#define WRITE_RVC_RS1S(value) WRITE_REG(insn.rvc_rs1s(), value)
 #define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value)
 #define WRITE_RVC_FRS2S(value) WRITE_FREG(insn.rvc_rs2s(), value)
 #define RVC_RS1 READ_REG(insn.rvc_rs1())

riscv/insns/c_addi4spn.h

@@ -1,2 +1,3 @@
 require_extension('C');
+require(insn.rvc_addi4spn_imm() != 0);
 WRITE_RVC_RS2S(sext_xlen(RVC_SP + insn.rvc_addi4spn_imm()));

riscv/insns/c_addiw.h

@@ -1,3 +0,0 @@
-require_extension('C');
-require_rv64;
-WRITE_RD(sext32(RVC_RS1 + insn.rvc_imm()));

riscv/insns/c_addw.h

@@ -1,3 +1,3 @@
 require_extension('C');
 require_rv64;
-WRITE_RD(sext32(RVC_RS1 + RVC_RS2));
+WRITE_RVC_RS1S(sext32(RVC_RS1S + RVC_RS2S));

riscv/insns/c_and.h

@@ -0,0 +1,2 @@
+require_extension('C');
+WRITE_RVC_RS1S(RVC_RS1S & RVC_RS2S);

riscv/insns/c_andi.h

@@ -0,0 +1,2 @@
+require_extension('C');
+WRITE_RVC_RS1S(RVC_RS1S & insn.rvc_imm());

riscv/insns/c_flw.h

@@ -3,6 +3,6 @@ if (xlen == 32) {
   require_extension('F');
   require_fp;
   WRITE_RVC_FRS2S(MMU.load_int32(RVC_RS1S + insn.rvc_lw_imm()));
-} else {
+} else { // c.ld
   WRITE_RVC_RS2S(MMU.load_int64(RVC_RS1S + insn.rvc_ld_imm()));
 }

riscv/insns/c_flwsp.h

@@ -3,7 +3,7 @@ if (xlen == 32) {
   require_extension('F');
   require_fp;
   WRITE_FRD(MMU.load_int32(RVC_SP + insn.rvc_lwsp_imm()));
-} else {
+} else { // c.ldsp
   require(insn.rvc_rd() != 0);
   WRITE_RD(MMU.load_int64(RVC_SP + insn.rvc_ldsp_imm()));
 }

riscv/insns/c_fsw.h

@@ -3,6 +3,6 @@ if (xlen == 32) {
   require_extension('F');
   require_fp;
   MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S);
-} else {
+} else { // c.sd
   MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S);
 }

riscv/insns/c_fswsp.h

@@ -3,6 +3,6 @@ if (xlen == 32) {
   require_extension('F');
   require_fp;
   MMU.store_uint32(RVC_SP + insn.rvc_swsp_imm(), RVC_FRS2);
-} else {
+} else { // c.sdsp
   MMU.store_uint64(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2);
 }

riscv/insns/c_jal.h

@@ -1,4 +1,8 @@
 require_extension('C');
-reg_t tmp = npc;
-set_pc(pc + insn.rvc_j_imm());
-WRITE_REG(X_RA, tmp);
+if (xlen == 32) {
+  reg_t tmp = npc;
+  set_pc(pc + insn.rvc_j_imm());
+  WRITE_REG(X_RA, tmp);
+} else {
+  WRITE_RD(sext32(RVC_RS1 + insn.rvc_imm()));
+}

riscv/insns/c_lbu.h

@@ -0,0 +1,2 @@
+require_extension('C');
+WRITE_RVC_RS2S(MMU.load_uint8(RVC_RS1S + insn.rvc_lb_imm()));

riscv/insns/c_or.h

@@ -0,0 +1,2 @@
+require_extension('C');
+WRITE_RVC_RS1S(RVC_RS1S | RVC_RS2S);

riscv/insns/c_sll.h

@@ -0,0 +1,2 @@
+require_extension('C');
+WRITE_RVC_RS1S(sext_xlen(RVC_RS1S << (RVC_RS2S & (xlen-1))));

riscv/insns/c_slli.h

@@ -1,3 +1,3 @@
 require_extension('C');
-require(insn.rvc_imm() < xlen);
-WRITE_RD(sext_xlen(RVC_RS1 << insn.rvc_imm()));
+require(insn.rvc_zimm() < xlen);
+WRITE_RD(sext_xlen(RVC_RS1 << insn.rvc_zimm()));

riscv/insns/c_srai.h

@@ -0,0 +1,3 @@
+require_extension('C');
+require(insn.rvc_zimm() < xlen);
+WRITE_RVC_RS1S(sext_xlen(sext_xlen(RVC_RS1S) >> insn.rvc_zimm()));

riscv/insns/c_srl.h

@@ -0,0 +1,2 @@
+require_extension('C');
+WRITE_RVC_RS1S(sext_xlen(zext_xlen(RVC_RS1S) >> (RVC_RS2S & (xlen-1))));

riscv/insns/c_srli.h

@@ -0,0 +1,3 @@
+require_extension('C');
+require(insn.rvc_zimm() < xlen);
+WRITE_RVC_RS1S(sext_xlen(zext_xlen(RVC_RS1S) >> insn.rvc_zimm()));

riscv/insns/c_sub.h

@@ -0,0 +1,2 @@
+require_extension('C');
+WRITE_RVC_RS1S(sext_xlen(RVC_RS1S - RVC_RS2S));

riscv/insns/c_subw.h

@@ -0,0 +1,3 @@
+require_extension('C');
+require_rv64;
+WRITE_RVC_RS1S(sext32(RVC_RS1S - RVC_RS2S));

riscv/insns/c_xor.h

@@ -0,0 +1,2 @@
+require_extension('C');
+WRITE_RVC_RS1S(RVC_RS1S ^ RVC_RS2S);

riscv/riscv.mk.in

@@ -84,8 +84,9 @@ riscv_insn_list = \
 	c_addi16sp \
 	c_addi4spn \
 	c_addi \
-	c_addiw \
 	c_addw \
+	c_and \
+	c_andi \
 	c_beqz \
 	c_bnez \
 	c_ebreak \
@@ -103,10 +104,19 @@ riscv_insn_list = \
 	c_jr \
 	c_li \
 	c_lui \
+	c_lbu \
 	c_lw \
 	c_lwsp \
 	c_mv \
+	c_or \
+	c_sll \
 	c_slli \
+	c_srai \
+	c_srl \
+	c_srli \
+	c_sub \
+	c_subw \
+	c_xor \
 	csrrc \
 	csrrci \
 	csrrs \

spike_main/disasm.cc

@@ -212,6 +212,12 @@ struct : public arg_t {
   }
 } rvc_sdsp_address;
 
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return std::to_string((int)insn.rvc_lb_imm()) + '(' + xpr_name[insn.rvc_rs1s()] + ')';
+  }
+} rvc_lb_address;
+
 struct : public arg_t {
   std::string to_string(insn_t insn) const {
     return std::to_string((int)insn.rvc_lw_imm()) + '(' + xpr_name[insn.rvc_rs1s()] + ')';
@@ -504,13 +510,21 @@ disassembler_t::disassembler_t()
   DISASM_INSN("addi", c_addi, 0, {&xrd, &xrd, &rvc_imm});
   DISASM_INSN("addiw", c_addiw, 0, {&xrd, &xrd, &rvc_imm});
   DISASM_INSN("slli", c_slli, 0, {&xrd, &rvc_shamt});
-  DISASM_INSN("mv", c_mv, 0, {&xrd, &rvc_rs1});
-  DISASM_INSN("add", c_add, 0, {&xrd, &xrd, &rvc_rs1});
-  DISASM_INSN("addw", c_addw, 0, {&xrd, &xrd, &rvc_rs1});
+  DISASM_INSN("mv", c_mv, 0, {&xrd, &rvc_rs2});
+  DISASM_INSN("add", c_add, 0, {&xrd, &xrd, &rvc_rs2});
+  DISASM_INSN("addw", c_addw, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_rs2s});
+  DISASM_INSN("sub", c_sub, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_rs2s});
+  DISASM_INSN("subw", c_subw, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_rs2s});
+  DISASM_INSN("and", c_and, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_rs2s});
+  DISASM_INSN("or", c_or, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_rs2s});
+  DISASM_INSN("xor", c_xor, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_rs2s});
+  DISASM_INSN("sll", c_sll, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_rs2s});
+  DISASM_INSN("srl", c_srl, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_rs2s});
   DISASM_INSN("lw", c_lwsp, 0, {&xrd, &rvc_lwsp_address});
   DISASM_INSN("flw", c_flwsp, 0, {&xrd, &rvc_lwsp_address});
   DISASM_INSN("sw", c_swsp, 0, {&rvc_rs2, &rvc_swsp_address});
   DISASM_INSN("fsw", c_fswsp, 0, {&rvc_rs2, &rvc_swsp_address});
+  DISASM_INSN("lbu", c_lbu, 0, {&rvc_rs2s, &rvc_lb_address});
   DISASM_INSN("lw", c_lw, 0, {&rvc_rs2s, &rvc_lw_address});
   DISASM_INSN("flw", c_flw, 0, {&rvc_rs2s, &rvc_lw_address});
   DISASM_INSN("sw", c_sw, 0, {&rvc_rs2s, &rvc_lw_address});