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riscv-isa-sim
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[xcc,pk,opcodes,sim] updated encoding/insn names

cs250
Andrew Waterman 16 years ago
parent
d17ab96ab5
commit
3fb2ead615
16 changed files with 241 additions and 143 deletions
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  1. 334
      riscv/execute.h
  2. 1
      riscv/insns/break.h
  3. 0
      riscv/insns/fence.h
  4. 0
      riscv/insns/fence_i.h
  5. 4
      riscv/insns/fmax_d.h
  6. 4
      riscv/insns/fmax_s.h
  7. 6
      riscv/insns/fmaxmag_d.h
  8. 6
      riscv/insns/fmaxmag_s.h
  9. 4
      riscv/insns/fmin_d.h
  10. 4
      riscv/insns/fmin_s.h
  11. 6
      riscv/insns/fminmag_d.h
  12. 6
      riscv/insns/fminmag_s.h
  13. 2
      riscv/insns/mtfsr.h
  14. 2
      riscv/processor.cc
  15. 2
      riscv/sim.cc
  16. 3
      riscv/trap.h

334
riscv/execute.h
View File

@ -152,53 +152,6 @@ switch((insn.bits >> 0x0) & 0x7f)
}
break;
}
case 0x17:
{
switch((insn.bits >> 0x7) & 0x7)
{
case 0x0:
{
if((insn.bits & 0x7ffffff) == 0x17)
{
#include "insns/rdnpc.h"
break;
}
#include "insns/unimp.h"
}
case 0x1:
{
if((insn.bits & 0xffffffff) == 0x97)
{
#include "insns/synci.h"
break;
}
#include "insns/unimp.h"
}
case 0x2:
{
if((insn.bits & 0xffffffff) == 0x117)
{
#include "insns/sync.h"
break;
}
#include "insns/unimp.h"
}
case 0x3:
{
if((insn.bits & 0xffc003ff) == 0x197)
{
#include "insns/syscall.h"
break;
}
#include "insns/unimp.h"
}
default:
{
#include "insns/unimp.h"
}
}
break;
}
case 0x1b:
{
switch((insn.bits >> 0x7) & 0x7)
@ -290,6 +243,27 @@ switch((insn.bits >> 0x0) & 0x7f)
}
break;
}
case 0x2f:
{
switch((insn.bits >> 0x7) & 0x7)
{
case 0x1:
{
#include "insns/fence_i.h"
break;
}
case 0x2:
{
#include "insns/fence.h"
break;
}
default:
{
#include "insns/unimp.h"
}
}
break;
}
case 0x33:
{
switch((insn.bits >> 0x7) & 0x7)
@ -696,14 +670,14 @@ switch((insn.bits >> 0x0) & 0x7f)
#include "insns/fcvt_lu_s.h"
break;
}
if((insn.bits & 0x3ff1ff) == 0x11053)
if((insn.bits & 0x1ffff) == 0x18053)
{
#include "insns/fcvt_s_d.h"
#include "insns/fmin_s.h"
break;
}
if((insn.bits & 0x1f1ff) == 0x53)
if((insn.bits & 0x3ff1ff) == 0x11053)
{
#include "insns/fadd_s.h"
#include "insns/fcvt_s_d.h"
break;
}
if((insn.bits & 0x3ff1ff) == 0xe053)
@ -711,16 +685,36 @@ switch((insn.bits >> 0x0) & 0x7f)
#include "insns/fcvt_s_w.h"
break;
}
if((insn.bits & 0x7c1ffff) == 0x1c053)
{
#include "insns/mftx_s.h"
break;
}
if((insn.bits & 0x3ff1ff) == 0x8053)
{
#include "insns/fcvt_l_s.h"
break;
}
if((insn.bits & 0x1ffff) == 0x17053)
{
#include "insns/fle_s.h"
break;
}
if((insn.bits & 0x7ffffff) == 0x1d053)
{
#include "insns/mffsr.h"
break;
}
if((insn.bits & 0x1f1ff) == 0x3053)
{
#include "insns/fdiv_s.h"
break;
}
if((insn.bits & 0x3fffff) == 0x1f053)
{
#include "insns/mtfsr.h"
break;
}
if((insn.bits & 0x3ff1ff) == 0xd053)
{
#include "insns/fcvt_s_lu.h"
@ -731,6 +725,26 @@ switch((insn.bits >> 0x0) & 0x7f)
#include "insns/fmul_s.h"
break;
}
if((insn.bits & 0x1ffff) == 0x16053)
{
#include "insns/flt_s.h"
break;
}
if((insn.bits & 0x1ffff) == 0x15053)
{
#include "insns/feq_s.h"
break;
}
if((insn.bits & 0x1ffff) == 0x7053)
{
#include "insns/fsgnjx_s.h"
break;
}
if((insn.bits & 0x1ffff) == 0x19053)
{
#include "insns/fmax_s.h"
break;
}
if((insn.bits & 0x3ff1ff) == 0xb053)
{
#include "insns/fcvt_wu_s.h"
@ -741,11 +755,21 @@ switch((insn.bits >> 0x0) & 0x7f)
#include "insns/fcvt_w_s.h"
break;
}
if((insn.bits & 0x3fffff) == 0x1e053)
{
#include "insns/mxtf_s.h"
break;
}
if((insn.bits & 0x1f1ff) == 0x1053)
{
#include "insns/fsub_s.h"
break;
}
if((insn.bits & 0x1ffff) == 0x5053)
{
#include "insns/fsgnj_s.h"
break;
}
if((insn.bits & 0x3ff1ff) == 0xf053)
{
#include "insns/fcvt_s_wu.h"
@ -761,176 +785,158 @@ switch((insn.bits >> 0x0) & 0x7f)
#include "insns/fsqrt_s.h"
break;
}
#include "insns/unimp.h"
}
case 0x1:
{
if((insn.bits & 0x3ff1ff) == 0xc0d3)
if((insn.bits & 0x1ffff) == 0x6053)
{
#include "insns/fcvt_d_l.h"
break;
}
if((insn.bits & 0x3ff1ff) == 0x100d3)
{
#include "insns/fcvt_d_s.h"
#include "insns/fsgnjn_s.h"
break;
}
if((insn.bits & 0x3ff1ff) == 0x80d3)
if((insn.bits & 0x1ffff) == 0x1b053)
{
#include "insns/fcvt_l_d.h"
#include "insns/fmaxmag_s.h"
break;
}
if((insn.bits & 0x1f1ff) == 0x20d3)
if((insn.bits & 0x1f1ff) == 0x53)
{
#include "insns/fmul_d.h"
#include "insns/fadd_s.h"
break;
}
if((insn.bits & 0x3ff1ff) == 0xb0d3)
if((insn.bits & 0x1ffff) == 0x1a053)
{
#include "insns/fcvt_wu_d.h"
#include "insns/fminmag_s.h"
break;
}
if((insn.bits & 0x3ff1ff) == 0xd0d3)
{
#include "insns/fcvt_d_lu.h"
break;
}
if((insn.bits & 0x3ff1ff) == 0xa0d3)
#include "insns/unimp.h"
}
case 0x1:
{
if((insn.bits & 0x1ffff) == 0x180d3)
{
#include "insns/fcvt_w_d.h"
#include "insns/fmin_d.h"
break;
}
if((insn.bits & 0x1f1ff) == 0xd3)
if((insn.bits & 0x3ff1ff) == 0xc0d3)
{
#include "insns/fadd_d.h"
#include "insns/fcvt_d_l.h"
break;
}
if((insn.bits & 0x3ff1ff) == 0x90d3)
if((insn.bits & 0x3fffff) == 0xe0d3)
{
#include "insns/fcvt_lu_d.h"
#include "insns/fcvt_d_w.h"
break;
}
if((insn.bits & 0x1f1ff) == 0x10d3)
if((insn.bits & 0x3ff1ff) == 0x100d3)
{
#include "insns/fsub_d.h"
#include "insns/fcvt_d_s.h"
break;
}
if((insn.bits & 0x3ff1ff) == 0x40d3)
if((insn.bits & 0x1ffff) == 0x190d3)
{
#include "insns/fsqrt_d.h"
#include "insns/fmax_d.h"
break;
}
if((insn.bits & 0x1f1ff) == 0x30d3)
if((insn.bits & 0x7c1ffff) == 0x1c0d3)
{
#include "insns/fdiv_d.h"
#include "insns/mftx_d.h"
break;
}
#include "insns/unimp.h"
}
case 0x4:
{
if((insn.bits & 0xf83fffff) == 0x1de53)
if((insn.bits & 0x1ffff) == 0x170d3)
{
#include "insns/mtfsr.h"
#include "insns/fle_d.h"
break;
}
if((insn.bits & 0x7c1ffff) == 0x18e53)
if((insn.bits & 0x1ffff) == 0x1b0d3)
{
#include "insns/mftx_s.h"
#include "insns/fmaxmag_d.h"
break;
}
if((insn.bits & 0x1ffff) == 0x17e53)
if((insn.bits & 0x1ffff) == 0x160d3)
{
#include "insns/fle_s.h"
#include "insns/flt_d.h"
break;
}
if((insn.bits & 0x7ffffff) == 0x1be53)
if((insn.bits & 0x1f1ff) == 0x20d3)
{
#include "insns/mffsr.h"
#include "insns/fmul_d.h"
break;
}
if((insn.bits & 0x1ffff) == 0x16e53)
if((insn.bits & 0x1ffff) == 0x70d3)
{
#include "insns/flt_s.h"
#include "insns/fsgnjx_d.h"
break;
}
if((insn.bits & 0x1ffff) == 0x15e53)
if((insn.bits & 0x1ffff) == 0x150d3)
{
#include "insns/feq_s.h"
#include "insns/feq_d.h"
break;
}
if((insn.bits & 0x1ffff) == 0x7e53)
if((insn.bits & 0x3fffff) == 0xf0d3)
{
#include "insns/fsgnjx_s.h"
#include "insns/fcvt_d_wu.h"
break;
}
if((insn.bits & 0x3fffff) == 0x1ce53)
if((insn.bits & 0x3ff1ff) == 0xb0d3)
{
#include "insns/mxtf_s.h"
#include "insns/fcvt_wu_d.h"
break;
}
if((insn.bits & 0x1ffff) == 0x5e53)
if((insn.bits & 0x1ffff) == 0x60d3)
{
#include "insns/fsgnj_s.h"
#include "insns/fsgnjn_d.h"
break;
}
if((insn.bits & 0x1ffff) == 0x6e53)
if((insn.bits & 0x3ff1ff) == 0xd0d3)
{
#include "insns/fsgnjn_s.h"
#include "insns/fcvt_d_lu.h"
break;
}
#include "insns/unimp.h"
}
case 0x5:
{
if((insn.bits & 0x3fffff) == 0xeed3)
if((insn.bits & 0x3ff1ff) == 0xa0d3)
{
#include "insns/fcvt_d_w.h"
#include "insns/fcvt_w_d.h"
break;
}
if((insn.bits & 0x7c1ffff) == 0x18ed3)
if((insn.bits & 0x3fffff) == 0x1e0d3)
{
#include "insns/mftx_d.h"
#include "insns/mxtf_d.h"
break;
}
if((insn.bits & 0x1ffff) == 0x17ed3)
if((insn.bits & 0x1ffff) == 0x1a0d3)
{
#include "insns/fle_d.h"
#include "insns/fminmag_d.h"
break;
}
if((insn.bits & 0x1ffff) == 0x16ed3)
if((insn.bits & 0x1ffff) == 0x50d3)
{
#include "insns/flt_d.h"
#include "insns/fsgnj_d.h"
break;
}
if((insn.bits & 0x1ffff) == 0x7ed3)
if((insn.bits & 0x3ff1ff) == 0x80d3)
{
#include "insns/fsgnjx_d.h"
#include "insns/fcvt_l_d.h"
break;
}
if((insn.bits & 0x1ffff) == 0x15ed3)
if((insn.bits & 0x1f1ff) == 0xd3)
{
#include "insns/feq_d.h"
#include "insns/fadd_d.h"
break;
}
if((insn.bits & 0x3fffff) == 0xfed3)
if((insn.bits & 0x3ff1ff) == 0x90d3)
{
#include "insns/fcvt_d_wu.h"
#include "insns/fcvt_lu_d.h"
break;
}
if((insn.bits & 0x1ffff) == 0x6ed3)
if((insn.bits & 0x1f1ff) == 0x10d3)
{
#include "insns/fsgnjn_d.h"
#include "insns/fsub_d.h"
break;
}
if((insn.bits & 0x3fffff) == 0x1ced3)
if((insn.bits & 0x3ff1ff) == 0x40d3)
{
#include "insns/mxtf_d.h"
#include "insns/fsqrt_d.h"
break;
}
if((insn.bits & 0x1ffff) == 0x5ed3)
if((insn.bits & 0x1f1ff) == 0x30d3)
{
#include "insns/fsgnj_d.h"
#include "insns/fdiv_d.h"
break;
}
#include "insns/unimp.h"
@ -1007,6 +1013,15 @@ switch((insn.bits >> 0x0) & 0x7f)
#include "insns/jalr_j.h"
break;
}
case 0x4:
{
if((insn.bits & 0x7ffffff) == 0x26b)
{
#include "insns/rdnpc.h"
break;
}
#include "insns/unimp.h"
}
default:
{
#include "insns/unimp.h"
@ -1019,18 +1034,42 @@ switch((insn.bits >> 0x0) & 0x7f)
#include "insns/jal.h"
break;
}
case 0x7f:
case 0x77:
{
switch((insn.bits >> 0x7) & 0x7)
{
case 0x0:
{
if((insn.bits & 0x7ffffff) == 0x47f)
if((insn.bits & 0xffffffff) == 0x77)
{
#include "insns/di.h"
#include "insns/syscall.h"
break;
}
#include "insns/unimp.h"
}
case 0x1:
{
if((insn.bits & 0xffffffff) == 0xf7)
{
#include "insns/break.h"
break;
}
if((insn.bits & 0x7ffffff) == 0x7f)
#include "insns/unimp.h"
}
default:
{
#include "insns/unimp.h"
}
}
break;
}
case 0x7b:
{
switch((insn.bits >> 0x7) & 0x7)
{
case 0x0:
{
if((insn.bits & 0x7ffffff) == 0x7b)
{
#include "insns/ei.h"
break;
@ -1039,21 +1078,34 @@ switch((insn.bits >> 0x0) & 0x7f)
}
case 0x1:
{
if((insn.bits & 0x7c1ffff) == 0xff)
if((insn.bits & 0x7ffffff) == 0xfb)
{
#include "insns/di.h"
break;
}
#include "insns/unimp.h"
}
case 0x2:
{
if((insn.bits & 0x7c1ffff) == 0x17b)
{
#include "insns/mfpcr.h"
break;
}
if((insn.bits & 0xf801ffff) == 0x4ff)
#include "insns/unimp.h"
}
case 0x3:
{
if((insn.bits & 0xf801ffff) == 0x1fb)
{
#include "insns/mtpcr.h"
break;
}
#include "insns/unimp.h"
}
case 0x2:
case 0x4:
{
if((insn.bits & 0xffffffff) == 0x17f)
if((insn.bits & 0xffffffff) == 0x27b)
{
#include "insns/eret.h"
break;

1
riscv/insns/break.h
View File

@ -0,0 +1 @@
throw trap_breakpoint;

0
riscv/insns/sync.h → riscv/insns/fence.h
View File

0
riscv/insns/synci.h → riscv/insns/fence_i.h
View File

4
riscv/insns/fmax_d.h
View File

@ -0,0 +1,4 @@
require_fp;
FRD = isNaNF64UI(FRS2) || f64_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */
? FRS1 : FRS2;
set_fp_exceptions;

4
riscv/insns/fmax_s.h
View File

@ -0,0 +1,4 @@
require_fp;
FRD = isNaNF32UI(FRS2) || f32_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */
? FRS1 : FRS2;
set_fp_exceptions;

6
riscv/insns/fmaxmag_d.h
View File

@ -0,0 +1,6 @@
require_fp;
uint64_t abs1 = FRS1 & ~INT64_MIN;
uint64_t abs2 = FRS2 & ~INT64_MIN;
FRD = isNaNF64UI(FRS2) || f64_le_quiet(abs2,abs1) /* && FRS1 not NaN */
? FRS1 : FRS2;
set_fp_exceptions;

6
riscv/insns/fmaxmag_s.h
View File

@ -0,0 +1,6 @@
require_fp;
uint32_t abs1 = FRS1 & ~INT32_MIN;
uint32_t abs2 = FRS2 & ~INT32_MIN;
FRD = isNaNF32UI(FRS2) || f32_le_quiet(abs2,abs1) /* && FRS1 not NaN */
? FRS1 : FRS2;
set_fp_exceptions;

4
riscv/insns/fmin_d.h
View File

@ -0,0 +1,4 @@
require_fp;
FRD = isNaNF64UI(FRS2) || f64_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */
? FRS1 : FRS2;
set_fp_exceptions;

4
riscv/insns/fmin_s.h
View File

@ -0,0 +1,4 @@
require_fp;
FRD = isNaNF32UI(FRS2) || f32_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */
? FRS1 : FRS2;
set_fp_exceptions;

6
riscv/insns/fminmag_d.h
View File

@ -0,0 +1,6 @@
require_fp;
uint64_t abs1 = FRS1 & ~INT64_MIN;
uint64_t abs2 = FRS2 & ~INT64_MIN;
FRD = isNaNF64UI(FRS2) || f64_lt_quiet(abs1,abs2) /* && FRS1 not NaN */
? FRS1 : FRS2;
set_fp_exceptions;

6
riscv/insns/fminmag_s.h
View File

@ -0,0 +1,6 @@
require_fp;
uint32_t abs1 = FRS1 & ~INT32_MIN;
uint32_t abs2 = FRS2 & ~INT32_MIN;
FRD = isNaNF32UI(FRS2) || f32_lt_quiet(abs1,abs2) /* && FRS1 not NaN */
? FRS1 : FRS2;
set_fp_exceptions;

2
riscv/insns/mtfsr.h
View File

@ -1,2 +1,4 @@
require_fp;
uint32_t tmp = fsr;
set_fsr(RS1);
RD = tmp;

2
riscv/processor.cc
View File

@ -8,6 +8,8 @@
#include "config.h"
#include "sim.h"
#include "softfloat.h"
#include "platform.h" // softfloat isNaNF32UI, etc.
#include "internals.h" // ditto
processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
: sim(_sim), mmu(_mem,_memsz)

2
riscv/sim.cc
View File

@ -109,7 +109,7 @@ void sim_t::interactive_run_silent(const std::string& cmd, const std::vector<std
void sim_t::interactive_run(const std::string& cmd, const std::vector<std::string>& args, bool noisy)
{
if(args.size())
step_all(atoi(args[0].c_str()),1,noisy);
step_all(atoll(args[0].c_str()),1,noisy);
else
while(1) step_all(1,1,noisy);
}

3
riscv/trap.h
View File

@ -7,8 +7,9 @@
DECLARE_TRAP(illegal_instruction), \
DECLARE_TRAP(privileged_instruction), \
DECLARE_TRAP(fp_disabled), \
DECLARE_TRAP(syscall), \
DECLARE_TRAP(interrupt), \
DECLARE_TRAP(syscall), \
DECLARE_TRAP(breakpoint), \
DECLARE_TRAP(data_address_misaligned), \
DECLARE_TRAP(load_access_fault), \
DECLARE_TRAP(store_access_fault), \

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