From aa074f2ab07d799eb9404688ac24088a9fff980c Mon Sep 17 00:00:00 2001 From: Parshintsev Anatoly Date: Thu, 6 Mar 2025 12:30:04 +0300 Subject: [PATCH] increase DTMCS.abits to be compliant debug specification ROI from "The RISC-V Debug Specification" (1.0) ``` 3.1. Debug Module Interface (DMI) ... The DMI uses between 7 and 32 address bits. ... ``` NOTE: RISC-V External Debug Specification 0.13.2 has the same sentence. --- riscv/jtag_dtm.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/riscv/jtag_dtm.h b/riscv/jtag_dtm.h index 23a54be1..bc681de7 100644 --- a/riscv/jtag_dtm.h +++ b/riscv/jtag_dtm.h @@ -51,7 +51,9 @@ class jtag_dtm_t // abits must come before dtmcontrol so it can easily be used in the // constructor. - const unsigned abits = 6; + // From RISC-V Debug Spec (both 0.13.2 and 1.0): + // The DMI uses between 7 and 32 address bits. + const unsigned abits = 7; uint32_t dtmcontrol; uint64_t dmi; unsigned bypass;