Daniel Lustig
5 years ago
committed by
GitHub
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3 changed files with
3 additions and
3 deletions
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README.md
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riscv/encoding.h
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riscv/mmu.cc
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@ -25,7 +25,7 @@ Spike supports the following RISC-V ISA features: |
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- Conformance to both RVWMO and RVTSO (Spike is sequentially consistent) |
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- Machine, Supervisor, and User modes, v1.11 |
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- Hypervisor extension, v0.6.1 |
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- Zsn extension, v0.1 |
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- Svnapot extension, v0.1 |
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- Debug v0.14 |
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Versioning and APIs |
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@ -227,7 +227,7 @@ |
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#define PTE_A 0x040 /* Accessed */ |
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#define PTE_D 0x080 /* Dirty */ |
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#define PTE_SOFT 0x300 /* Reserved for Software */ |
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#define PTE_N 0x4000000000000000 /* Zsn: NAPOT translation contiguity */ |
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#define PTE_N 0x4000000000000000 /* Svnapot: NAPOT translation contiguity */ |
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#define PTE_PPN_SHIFT 10 |
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@ -432,7 +432,7 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode, bool virt, bool mxr) |
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if ((pte & ad) != ad) |
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break; |
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#endif |
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// for superpage or Zsn NAPOT mappings, make a fake leaf PTE for the TLB's benefit.
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// for superpage or Svnapot NAPOT mappings, make a fake leaf PTE for the TLB's benefit.
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reg_t vpn = addr >> PGSHIFT; |
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int napot_bits = ((pte & PTE_N) ? (ctz(ppn) + 1) : 0); |
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