revamp hwacha; now runs in physical mode

configure

@@ -4241,6 +4241,51 @@ fi
 
 
 
+    # Add subproject to our running list
+
+    subprojects="$subprojects hwacha"
+
+    # Process the subproject appropriately. If enabled add it to the
+    # $enabled_subprojects running shell variable, set a
+    # SUBPROJECT_ENABLED C define, and include the appropriate
+    # 'subproject.ac'.
+
+
+      { $as_echo "$as_me:${as_lineno-$LINENO}: configuring default subproject : hwacha" >&5
+$as_echo "$as_me: configuring default subproject : hwacha" >&6;}
+      ac_config_files="$ac_config_files hwacha.mk:hwacha/hwacha.mk.in"
+
+      enable_hwacha_sproj="yes"
+      subprojects_enabled="$subprojects_enabled hwacha"
+
+$as_echo "#define HWACHA_ENABLED /**/" >>confdefs.h
+
+
+
+
+
+
+    # Determine if this is a required or an optional subproject
+
+
+
+    # Determine if there is a group with the same name
+
+
+
+    # Create variations of the subproject name suitable for use as a CPP
+    # enabled define, a shell enabled variable, and a shell function
+
+
+
+
+
+
+
+
+
+
+
     # Add subproject to our running list
 
     subprojects="$subprojects softfloat"
@@ -5039,6 +5084,7 @@ for ac_config_target in $ac_config_targets
 do
   case $ac_config_target in
     "riscv.mk") CONFIG_FILES="$CONFIG_FILES riscv.mk:riscv/riscv.mk.in" ;;
+    "hwacha.mk") CONFIG_FILES="$CONFIG_FILES hwacha.mk:hwacha/hwacha.mk.in" ;;
     "softfloat.mk") CONFIG_FILES="$CONFIG_FILES softfloat.mk:softfloat/softfloat.mk.in" ;;
     "softfloat_riscv.mk") CONFIG_FILES="$CONFIG_FILES softfloat_riscv.mk:softfloat_riscv/softfloat_riscv.mk.in" ;;
     "config.h") CONFIG_HEADERS="$CONFIG_HEADERS config.h" ;;

configure.ac

@@ -81,7 +81,7 @@ AC_SUBST([CXXFLAGS],["-Wall -O2 -std=c++0x"])
 # The '*' suffix indicates an optional subproject. The '**' suffix
 # indicates an optional subproject which is also the name of a group.
 
-MCPPBS_SUBPROJECTS([ riscv, softfloat, softfloat_riscv ])
+MCPPBS_SUBPROJECTS([ riscv, hwacha, softfloat, softfloat_riscv ])
 
 #-------------------------------------------------------------------------
 # MCPPBS subproject groups

hwacha/README

@@ -1,2 +1,2 @@
 This directory contains work in progress on Hwacha, a data-parallel
-accelerator.  It is not currently usable.
+accelerator.

hwacha/decode_hwacha.h

@@ -0,0 +1,64 @@
+#ifndef _DECODE_HWACHA_H
+#define _DECODE_HWACHA_H
+
+#define XS1 (xs1)
+#define XS2 (xs2)
+#define WRITE_XRD(value) (xd = value)
+
+#define NXPR (h->get_ct_state()->nxpr)
+#define NFPR (h->get_ct_state()->nfpr)
+#define MAXVL (h->get_ct_state()->maxvl)
+#define VL (h->get_ct_state()->vl)
+#define WRITE_NXPR(nxprnext) (h->get_ct_state()->nxpr = (nxprnext))
+#define WRITE_NFPR(nfprnext) (h->get_ct_state()->nfpr = (nfprnext))
+#define WRITE_MAXVL(maxvlnext) (h->get_ct_state()->maxvl = (maxvlnext))
+#define WRITE_VL(vlnext) (h->get_ct_state()->vl = (vlnext))
+
+#define INSN_RS1 (insn.rs1())
+#define INSN_RS2 (insn.rs2())
+#define INSN_RS3 (insn.rs3())
+#define INSN_RD (insn.rd())
+#define INSN_SEG ((insn.i_imm() >> 9)+1)
+
+#define UT_READ_XPR(idx, src) (h->get_ut_state(idx)->XPR[src])
+#define UT_WRITE_XPR(idx, dst, value) (h->get_ut_state(idx)->XPR.write(dst, value))
+#define UT_RS1(idx) (UT_READ_XPR(idx, INSN_RS1))
+#define UT_RS2(idx) (UT_READ_XPR(idx, INSN_RS2))
+#define UT_WRITE_RD(idx, value) (UT_WRITE_XPR(idx, INSN_RD, value))
+
+#define UT_READ_FPR(idx, src) (h->get_ut_state(idx)->FPR[src])
+#define UT_WRITE_FPR(idx, dst, value) (h->get_ut_state(idx)->FPR.write(dst, value))
+#define UT_FRS1(idx) (UT_READ_FPR(idx, INSN_RS1))
+#define UT_FRS2(idx) (UT_READ_FPR(idx, INSN_RS2))
+#define UT_FRS3(idx) (UT_READ_FPR(idx, INSN_RS3))
+#define UT_WRITE_FRD(idx, value) (UT_WRITE_FPR(idx, INSN_RD, value))
+
+#define VEC_SEG_LOAD(dst, func, inc) \
+  VEC_SEG_ST_LOAD(dst, func, INSN_SEG*inc, inc)
+
+#define VEC_SEG_ST_LOAD(dst, func, stride, inc) \
+  reg_t seg_addr = XS1; \
+  for (uint32_t i=0; i<VL; i++) { \
+    reg_t addr = seg_addr; \
+    seg_addr += stride; \
+    for (uint32_t j=0; j<INSN_SEG; j++) { \
+      UT_WRITE_##dst(i, INSN_RD+j, p->get_mmu()->func(addr)); \
+      addr += inc; \
+    } \
+  }
+
+#define VEC_SEG_STORE(src, func, inc) \
+  VEC_SEG_ST_STORE(src, func, INSN_SEG*inc, inc)
+
+#define VEC_SEG_ST_STORE(src, func, stride, inc) \
+  reg_t seg_addr = XS1; \
+  for (uint32_t i=0; i<VL; i++) { \
+    reg_t addr = seg_addr; \
+    seg_addr += stride; \
+    for (uint32_t j=0; j<INSN_SEG; j++) { \
+      p->get_mmu()->func(addr, UT_READ_##src(i, INSN_RD+j)); \
+      addr += inc; \
+    } \
+  }
+
+#endif

hwacha/decode_hwacha_ut.h

@@ -0,0 +1,34 @@
+#ifndef _DECODE_HWACHA_UT_H
+#define _DECODE_HWACHA_UT_H
+
+#include "decode_hwacha.h"
+
+#define UTIDX (i)
+
+#undef RS1
+#undef RS2
+#undef WRITE_RD
+
+#define RS1 UT_RS1(UTIDX)
+#define RS2 UT_RS2(UTIDX)
+#define WRITE_RD(value) UT_WRITE_RD(UTIDX, value)
+
+#undef FRS1
+#undef FRS2
+#undef FRS3
+#undef WRITE_FRD
+
+#define FRS1 UT_FRS1(UTIDX)
+#define FRS2 UT_FRS2(UTIDX)
+#define FRS3 UT_FRS3(UTIDX)
+#define WRITE_FRD(value) UT_WRITE_FRD(UTIDX, value)
+
+// we assume the vector unit has floating-point alus
+#undef require_fp
+#define require_fp
+
+// YUNSUP FIXME
+#undef set_fp_exceptions
+#define set_fp_exceptions
+
+#endif

hwacha/disasm.cc

@@ -1,72 +0,0 @@
-hwacha_disassembler::hwacha_disassembler()
-{
-  #define DEFINE_RS1(code) DISASM_INSN(#code, code, 0, xrs1_reg)
-  #define DEFINE_RS1_RS2(code) DISASM_INSN(#code, code, 0, xrs1_reg, xrs2_reg)
-  #define DEFINE_VEC_XMEM(code) DISASM_INSN(#code, code, 0, vxrd_reg, xrs1_reg)
-  #define DEFINE_VEC_XMEMST(code) DISASM_INSN(#code, code, 0, vxrd_reg, xrs1_reg, xrs2_reg)
-  #define DEFINE_VEC_FMEM(code) DISASM_INSN(#code, code, 0, vfrd_reg, xrs1_reg)
-  #define DEFINE_VEC_FMEMST(code) DISASM_INSN(#code, code, 0, vfrd_reg, xrs1_reg, xrs2_reg)
-
-  DEFINE_RS1(vxcptsave);
-  DEFINE_RS1(vxcptrestore);
-  DEFINE_NOARG(vxcptkill);
-
-  DEFINE_RS1(vxcptevac);
-  DEFINE_NOARG(vxcpthold);
-  DEFINE_RS1_RS2(venqcmd);
-  DEFINE_RS1_RS2(venqimm1);
-  DEFINE_RS1_RS2(venqimm2);
-  DEFINE_RS1_RS2(venqcnt);
-
-  DEFINE_VEC_XMEM(vld);
-  DEFINE_VEC_XMEM(vlw);
-  DEFINE_VEC_XMEM(vlwu);
-  DEFINE_VEC_XMEM(vlh);
-  DEFINE_VEC_XMEM(vlhu);
-  DEFINE_VEC_XMEM(vlb);
-  DEFINE_VEC_XMEM(vlbu);
-  DEFINE_VEC_FMEM(vfld);
-  DEFINE_VEC_FMEM(vflw);
-  DEFINE_VEC_XMEMST(vlstd);
-  DEFINE_VEC_XMEMST(vlstw);
-  DEFINE_VEC_XMEMST(vlstwu);
-  DEFINE_VEC_XMEMST(vlsth);
-  DEFINE_VEC_XMEMST(vlsthu);
-  DEFINE_VEC_XMEMST(vlstb);
-  DEFINE_VEC_XMEMST(vlstbu);
-  DEFINE_VEC_FMEMST(vflstd);
-  DEFINE_VEC_FMEMST(vflstw);
-
-  DEFINE_VEC_XMEM(vsd);
-  DEFINE_VEC_XMEM(vsw);
-  DEFINE_VEC_XMEM(vsh);
-  DEFINE_VEC_XMEM(vsb);
-  DEFINE_VEC_FMEM(vfsd);
-  DEFINE_VEC_FMEM(vfsw);
-  DEFINE_VEC_XMEMST(vsstd);
-  DEFINE_VEC_XMEMST(vsstw);
-  DEFINE_VEC_XMEMST(vssth);
-  DEFINE_VEC_XMEMST(vsstb);
-  DEFINE_VEC_FMEMST(vfsstd);
-  DEFINE_VEC_FMEMST(vfsstw);
-
-  DISASM_INSN("vmvv", vmvv, 0, vxrd_reg, vxrs1_reg);
-  DISASM_INSN("vmsv", vmsv, 0, vxrd_reg, xrs1_reg);
-  DISASM_INSN("vmst", vmst, 0, vxrd_reg, xrs1_reg, xrs2_reg);
-  DISASM_INSN("vmts", vmts, 0, xrd_reg, vxrs1_reg, xrs2_reg);
-  DISASM_INSN("vfmvv", vfmvv, 0, vfrd_reg, vfrs1_reg);
-  DISASM_INSN("vfmsv", vfmsv, 0, vfrd_reg, frs1_reg);
-  DISASM_INSN("vfmst", vfmst, 0, vfrd_reg, frs1_reg, frs2_reg);
-  DISASM_INSN("vfmts", vfmts, 0, frd_reg, vfrs1_reg, frs2_reg);
-
-  DEFINE_RS1_RS2(vvcfg);
-  DEFINE_RS1_RS2(vtcfg);
-
-  DISASM_INSN("vvcfgivl", vvcfgivl, 0, xrd_reg, xrs1_reg, nxregs_reg, nfregs_reg);
-  DISASM_INSN("vtcfgivl", vtcfgivl, 0, xrd_reg, xrs1_reg, nxregs_reg, nfregs_reg);
-  DISASM_INSN("vsetvl", vsetvl, 0, xrd_reg, xrs1_reg);
-  DISASM_INSN("vf", vf, 0, xrs1_reg, imm);
-
-  DEFINE_NOARG(fence_v_l);
-  DEFINE_NOARG(fence_v_g);
-}

hwacha/hwacha.cc

@@ -0,0 +1,46 @@
+#include "hwacha.h"
+
+void ct_state_t::reset()
+{
+  vl = 0;
+  maxvl = 32;
+  nxpr = 32;
+  nfpr = 32;
+
+  vf_pc = -1;
+}
+
+void ut_state_t::reset()
+{
+  run = false;
+  XPR.reset();
+  FPR.reset();
+}
+
+hwacha_t::hwacha_t()
+{
+  ct_state.reset();
+  for (int i=0; i<max_uts; i++)
+    ut_state[i].reset();
+}
+
+std::vector<insn_desc_t> hwacha_t::get_instructions()
+{
+  std::vector<insn_desc_t> insns;
+  #define DECLARE_INSN(name, match, mask) \
+    extern reg_t hwacha_##name(processor_t*, insn_t, reg_t); \
+    insns.push_back((insn_desc_t){match, mask, &::illegal_instruction, hwacha_##name});
+  #include "opcodes_hwacha.h"
+  #undef DECLARE_INSN
+  return insns;
+}
+
+bool hwacha_t::vf_active()
+{
+  for (int i=0; i<get_ct_state()->vl; i++) {
+    if (get_ut_state(i)->run)
+      return true;
+  }
+
+  return false;
+}

hwacha/hwacha.h

@@ -1,49 +1,45 @@
 #ifndef _HWACHA_H
 #define _HWACHA_H
 
-// vector stuff
-#define VL vl
-
-#define UT_RS1(idx) uts[idx]->XPR[insn.rtype.rs1]
-#define UT_RS2(idx) uts[idx]->XPR[insn.rtype.rs2]
-#define UT_RD(idx) uts[idx]->XPR.write_port(insn.rtype.rd)
-#define UT_RA(idx) uts[idx]->XPR.write_port(1)
-#define UT_FRS1(idx) uts[idx]->FPR[insn.ftype.rs1]
-#define UT_FRS2(idx) uts[idx]->FPR[insn.ftype.rs2]
-#define UT_FRS3(idx) uts[idx]->FPR[insn.ftype.rs3]
-#define UT_FRD(idx) uts[idx]->FPR.write_port(insn.ftype.rd)
-#define UT_RM(idx) ((insn.ftype.rm != 7) ? insn.ftype.rm : \
-              ((uts[idx]->fsr & FSR_RD) >> FSR_RD_SHIFT))
-
-#define UT_LOOP_START for (int i=0;i<VL; i++) {
-#define UT_LOOP_END }
-#define UT_LOOP_RS1 UT_RS1(i)
-#define UT_LOOP_RS2 UT_RS2(i)
-#define UT_LOOP_RD UT_RD(i)
-#define UT_LOOP_RA UT_RA(i)
-#define UT_LOOP_FRS1 UT_FRS1(i)
-#define UT_LOOP_FRS2 UT_FRS2(i)
-#define UT_LOOP_FRS3 UT_FRS3(i)
-#define UT_LOOP_FRD UT_FRD(i)
-#define UT_LOOP_RM UT_RM(i)
-
-#define VEC_LOAD(dst, func, inc) \
-  reg_t addr = RS1; \
-  UT_LOOP_START \
-    UT_LOOP_##dst = mmu.func(addr); \
-    addr += inc; \
-  UT_LOOP_END
-
-#define VEC_STORE(src, func, inc) \
-  reg_t addr = RS1; \
-  UT_LOOP_START \
-    mmu.func(addr, UT_LOOP_##src); \
-    addr += inc; \
-  UT_LOOP_END
-
-enum vt_command_t
+#include "extension.h"
+
+struct ct_state_t
+{
+  void reset();
+
+  uint32_t nxpr;
+  uint32_t nfpr;
+  uint32_t maxvl;
+  uint32_t vl;
+
+  reg_t vf_pc;
+};
+
+struct ut_state_t
 {
-  vt_command_stop,
+  void reset();
+
+  bool run;
+  regfile_t<reg_t, 32, true> XPR;
+  regfile_t<reg_t, 32, false> FPR;
+};
+
+class hwacha_t : public extension_t
+{
+public:
+  hwacha_t();
+  const char* name() { return "hwacha"; }
+  std::vector<insn_desc_t> get_instructions();
+  ct_state_t* get_ct_state() { return &ct_state; }
+  ut_state_t* get_ut_state(int idx) { return &ut_state[idx]; }
+  bool vf_active();
+
+private:
+  static const int max_uts = 2048;
+  ct_state_t ct_state;
+  ut_state_t ut_state[max_uts];
 };
 
+REGISTER_EXTENSION(hwacha, []() { return new hwacha_t; })
+
 #endif

hwacha/hwacha.mk.in

@@ -0,0 +1,35 @@
+get_insn_list = $(shell cat $(1) | sed 's/DECLARE_INSN(\(.*\),.*,.*)/\1/')
+get_opcode = $(shell grep \\\<$(2)\\\> $(1) | sed 's/DECLARE_INSN(.*,\(.*\),.*)/\1/')
+
+hwacha_subproject_deps = \
+	riscv \
+	softfloat \
+
+hwacha_install_prog_srcs = \
+
+hwacha_hdrs = \
+	hwacha.h \
+	decode_hwacha.h \
+	decode_hwacha_ut.h \
+	opcodes_hwacha.h \
+	opcodes_hwacha_ut.h \
+
+hwacha_srcs = \
+	hwacha.cc \
+	$(hwacha_gen_srcs) \
+	$(hwacha_ut_gen_srcs) \
+
+hwacha_test_srcs =
+
+hwacha_gen_srcs = \
+	$(addsuffix .cc, $(call get_insn_list,$(src_dir)/hwacha/opcodes_hwacha.h))
+
+$(hwacha_gen_srcs): %.cc: insns/%.h insn_template_hwacha.cc
+	sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/hwacha/insn_template_hwacha.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/hwacha/opcodes_hwacha.h,$(subst .cc,,$@))/' > $@
+
+hwacha_ut_gen_srcs = \
+	$(addsuffix .cc, $(call get_insn_list,$(src_dir)/hwacha/opcodes_hwacha_ut.h))
+
+$(hwacha_ut_gen_srcs): %.cc: insns_ut/%.h insn_template_hwacha_ut.cc
+	sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/hwacha/insn_template_hwacha_ut.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/hwacha/opcodes_hwacha_ut.h,$(subst .cc,,$@))/' > $@
+

hwacha/insn_template_hwacha.cc

@@ -0,0 +1,24 @@
+// See LICENSE for license details.
+
+#include "config.h"
+#include "processor.h"
+#include "mmu.h"
+#include "hwacha.h"
+#include "decode_hwacha.h"
+#include "rocc.h"
+#include <assert.h>
+
+reg_t hwacha_NAME(processor_t* p, insn_t insn, reg_t pc)
+{
+  int xprlen = 64;
+  reg_t npc = sext_xprlen(pc + insn_length(OPCODE));
+  hwacha_t* h = static_cast<hwacha_t*>(p->get_extension());
+  rocc_insn_union_t u;
+  u.i = insn;
+  reg_t xs1 = u.r.xs1 ? RS1 : -1;
+  reg_t xs2 = u.r.xs2 ? RS2 : -1;
+  reg_t xd = -1;
+  #include "insns/NAME.h"
+  if (u.r.xd) WRITE_RD(xd);
+  return npc;
+}

hwacha/insn_template_hwacha_ut.cc

@@ -0,0 +1,22 @@
+// See LICENSE for license details.
+
+#include "config.h"
+#include "processor.h"
+#include "mmu.h"
+#include "softfloat.h"
+#include "platform.h" // softfloat isNaNF32UI, etc.
+#include "internals.h" // ditto
+#include "hwacha.h"
+#include "decode_hwacha_ut.h"
+#include <assert.h>
+
+reg_t hwacha_NAME(processor_t* p, insn_t insn, reg_t pc)
+{
+  int xprlen = 64;
+  reg_t npc = sext_xprlen(pc + insn_length(OPCODE));
+  hwacha_t* h = static_cast<hwacha_t*>(p->get_extension());
+  for (uint32_t i=0; i<VL; i++) {
+    #include "insns_ut/NAME.h"
+  }
+  return npc;
+}

hwacha/insns/fmovn.h

@@ -1,2 +0,0 @@
-require_vector;
-if (RS1 & 0x1) FRD = FRS2;

hwacha/insns/fmovz.h

@@ -1,2 +0,0 @@
-require_vector;
-if (~RS1 & 0x1) FRD = FRS2;

hwacha/insns/movn.h

@@ -1,2 +0,0 @@
-require_vector;
-if (RS1 & 0x1) RD = RS2;

hwacha/insns/movz.h

@@ -1,2 +0,0 @@
-require_vector;
-if (~RS1 & 0x1) RD = RS2;

hwacha/insns/stop.h

@@ -1,3 +0,0 @@
-require_vector;
-utmode = false;
-throw vt_command_stop;

hwacha/insns/utidx.h

@@ -1,2 +0,0 @@
-require_vector;
-RD = utidx;

hwacha/insns/vf.h

@@ -1,9 +1,28 @@
-require_vector;
-for (int i=0; i<VL; i++)
-{
-  uts[i]->pc = ITYPE_EADDR;
-  uts[i]->utmode = true;
-  uts[i]->run = true;
-  while (uts[i]->utmode)
-    uts[i]->step(100, false); // XXX
+if (VL) {
+  if (!h->vf_active()) {
+    h->get_ct_state()->vf_pc = XS1 + insn.s_imm();
+    for (uint32_t i=0; i<VL; i++)
+      h->get_ut_state(i)->run = true;
+  }
+
+  mmu_t::insn_fetch_t ut_fetch = p->get_mmu()->load_insn(h->get_ct_state()->vf_pc);
+  insn_t ut_insn = ut_fetch.insn.insn;
+
+  bool matched = false;
+
+  #define DECLARE_INSN(name, match, mask) \
+    extern reg_t hwacha_##name(processor_t*, insn_t, reg_t); \
+    if ((ut_insn.bits() & mask) == match) { \
+      h->get_ct_state()->vf_pc = hwacha_##name(p, ut_insn, h->get_ct_state()->vf_pc); \
+      matched = true; \
+    }
+  #include "opcodes_hwacha_ut.h"
+  #undef DECLARE_INSN
+
+  // YUNSUP FIXME
+  assert(matched);
+
+  // if vf is still running, rewind pc so that it will execute again
+  if (h->vf_active())
+    npc = pc;
 }

hwacha/insns/vfld.h

@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_LOAD(FRD, load_int64, 8);

hwacha/insns/vflsegd.h

@@ -0,0 +1 @@
+VEC_SEG_LOAD(FPR, load_int64, 8);

hwacha/insns/vflsegstd.h

@@ -0,0 +1 @@
+VEC_SEG_ST_LOAD(FPR, load_int64, XS2, 8);

hwacha/insns/vflsegstw.h

@@ -0,0 +1 @@
+VEC_SEG_ST_LOAD(FPR, load_int32, XS2, 4);

hwacha/insns/vflsegw.h

@@ -0,0 +1 @@
+VEC_SEG_LOAD(FPR, load_int32, 4);

hwacha/insns/vflstd.h

@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_LOAD(FRD, load_int64, RS2);

hwacha/insns/vflstw.h

@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_LOAD(FRD, load_int32, RS2);

hwacha/insns/vflw.h

@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_LOAD(FRD, load_int32, 4);

hwacha/insns/vfmst.h

@@ -1,4 +0,0 @@
-require_vector;
-require_fp;
-assert(0 <= RS2 && RS2 < MAX_UTS);
-UT_FRD(RS2) = FRS1;

hwacha/insns/vfmsv.h

@@ -1,5 +0,0 @@
-require_vector;
-require_fp;
-UT_LOOP_START
-  UT_LOOP_FRD = FRS1;
-UT_LOOP_END

hwacha/insns/vfmts.h

@@ -1,4 +0,0 @@
-require_vector;
-require_fp;
-assert(0 <= RS2 && RS2 < MAX_UTS);
-FRD = UT_FRS1(RS2);

hwacha/insns/vfmvv.h

@@ -1,5 +0,0 @@
-require_vector;
-require_fp;
-UT_LOOP_START
-  UT_LOOP_FRD = UT_LOOP_FRS1;
-UT_LOOP_END

hwacha/insns/vfsd.h

@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_STORE(FRD, store_uint64, 8);

hwacha/insns/vfssegd.h

@@ -0,0 +1 @@
+VEC_SEG_STORE(FPR, store_uint64, 8);

hwacha/insns/vfssegstd.h

@@ -0,0 +1 @@
+VEC_SEG_ST_STORE(FPR, store_uint64, XS2, 8);

hwacha/insns/vfssegstw.h

@@ -0,0 +1 @@
+VEC_SEG_ST_STORE(FPR, store_uint32, XS2, 4);

hwacha/insns/vfssegw.h

@@ -0,0 +1 @@
+VEC_SEG_STORE(FPR, store_uint32, 4);

hwacha/insns/vfsstd.h

@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_STORE(FRD, store_uint64, RS2);

hwacha/insns/vfsstw.h

@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_STORE(FRD, store_uint32, RS2);

hwacha/insns/vfsw.h

@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_STORE(FRD, store_uint32, 4);

hwacha/insns/vgetcfg.h

@@ -0,0 +1 @@
+WRITE_XRD((NXPR & 0x3f) | ((NFPR & 0x3f) << 6));

hwacha/insns/vgetvl.h

@@ -0,0 +1 @@
+WRITE_XRD(VL);

hwacha/insns/vlb.h

@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_int8, 1);

hwacha/insns/vlbu.h

@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_uint8, 1);

hwacha/insns/vld.h

@@ -1,3 +0,0 @@
-require_vector;
-require_xpr64;
-VEC_LOAD(RD, load_int64, 8);

hwacha/insns/vlh.h

@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_int16, 2);

hwacha/insns/vlhu.h

@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_uint16, 2);

hwacha/insns/vlsegb.h

@@ -0,0 +1 @@
+VEC_SEG_LOAD(XPR, load_int8, 1);

hwacha/insns/vlsegbu.h

@@ -0,0 +1 @@
+VEC_SEG_LOAD(XPR, load_uint8, 1);

hwacha/insns/vlsegd.h

@@ -0,0 +1 @@
+VEC_SEG_LOAD(XPR, load_int64, 8);

hwacha/insns/vlsegh.h

@@ -0,0 +1 @@
+VEC_SEG_LOAD(XPR, load_int16, 2);

hwacha/insns/vlseghu.h

@@ -0,0 +1 @@
+VEC_SEG_LOAD(XPR, load_uint16, 2);

hwacha/insns/vlsegstb.h

@@ -0,0 +1 @@
+VEC_SEG_ST_LOAD(XPR, load_int8, XS2, 1);

hwacha/insns/vlsegstbu.h

@@ -0,0 +1 @@
+VEC_SEG_ST_LOAD(XPR, load_uint8, XS2, 1);

hwacha/insns/vlsegstd.h

@@ -0,0 +1 @@
+VEC_SEG_ST_LOAD(XPR, load_int64, XS2, 8);

hwacha/insns/vlsegsth.h

@@ -0,0 +1 @@
+VEC_SEG_ST_LOAD(XPR, load_int16, XS2, 2);

hwacha/insns/vlsegsthu.h

@@ -0,0 +1 @@
+VEC_SEG_ST_LOAD(XPR, load_uint16, XS2, 2);

hwacha/insns/vlsegstw.h

@@ -0,0 +1 @@
+VEC_SEG_ST_LOAD(XPR, load_int32, XS2, 4);

hwacha/insns/vlsegstwu.h

@@ -0,0 +1 @@
+VEC_SEG_ST_LOAD(XPR, load_uint32, XS2, 4);

hwacha/insns/vlsegw.h

@@ -0,0 +1 @@
+VEC_SEG_LOAD(XPR, load_int32, 4);

hwacha/insns/vlsegwu.h

@@ -0,0 +1 @@
+VEC_SEG_LOAD(XPR, load_uint32, 4);

hwacha/insns/vlstb.h

@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_int8, RS2);

hwacha/insns/vlstbu.h

@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_uint8, RS2);

hwacha/insns/vlstd.h

@@ -1,3 +0,0 @@
-require_vector;
-require_xpr64;
-VEC_LOAD(RD, load_int64, RS2);

hwacha/insns/vlsth.h

@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_int16, RS2);

hwacha/insns/vlsthu.h

@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_uint16, RS2);

hwacha/insns/vlstw.h

@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_int32, RS2);

hwacha/insns/vlstwu.h

@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_uint32, RS2);

hwacha/insns/vlw.h

@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_int32, 4);

hwacha/insns/vlwu.h

@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_uint32, 4);

hwacha/insns/vmst.h

@@ -1,3 +0,0 @@
-require_vector;
-assert(0 <= RS2 && RS2 < MAX_UTS);
-UT_RD(RS2) = RS1;

hwacha/insns/vmsv.h

@@ -1,4 +1,2 @@
-require_vector;
-UT_LOOP_START
-  UT_LOOP_RD = RS1;
-UT_LOOP_END
+for (uint32_t i=0; i<VL; i++)
+  UT_WRITE_RD(i, XS1);

hwacha/insns/vmts.h

@@ -1,3 +0,0 @@
-require_vector;
-assert(0 <= RS2 && RS2 < MAX_UTS);
-RD = UT_RS1(RS2);

hwacha/insns/vmvv.h

@@ -1,4 +1,3 @@
-require_vector;
-UT_LOOP_START
-  UT_LOOP_RD = UT_LOOP_RS1;
-UT_LOOP_END
+for (uint32_t i=0; i<VL; i++) {
+  UT_WRITE_RD(i, UT_RS1(i));
+}

hwacha/insns/vsb.h

@@ -1,2 +0,0 @@
-require_vector;
-VEC_STORE(RD, store_uint8, 1);

hwacha/insns/vsd.h

@@ -1,3 +0,0 @@
-require_vector;
-require_xpr64;
-VEC_STORE(RD, store_uint64, 8);

hwacha/insns/vsetcfg.h

@@ -0,0 +1,9 @@
+uint32_t nxpr = (XS1 & 0x3f) + (insn.i_imm() & 0x3f);
+uint32_t nfpr = ((XS1 >> 6) & 0x3f) + ((insn.i_imm() >> 6) & 0x3f);
+// YUNSUP FIXME
+// raise trap when nxpr/nfpr is larger than possible
+WRITE_NXPR(nxpr);
+WRITE_NFPR(nfpr);
+uint32_t maxvl = 8 * (256 / (nxpr-1 + nfpr));
+WRITE_MAXVL(maxvl);
+WRITE_VL(0);

hwacha/insns/vsetvl.h

@@ -1,3 +1,3 @@
-require_vector;
-setvl(RS1);
-RD = VL;
+uint32_t vl = std::min(MAXVL, (uint32_t)XS1);
+WRITE_VL(vl);
+WRITE_XRD(vl);

hwacha/insns/vsh.h

@@ -1,2 +0,0 @@
-require_vector;
-VEC_STORE(RD, store_uint16, 2);

hwacha/insns/vssegb.h

@@ -0,0 +1 @@
+VEC_SEG_STORE(XPR, store_uint8, 1);

hwacha/insns/vssegd.h

@@ -0,0 +1 @@
+VEC_SEG_STORE(XPR, store_uint64, 8);

hwacha/insns/vssegh.h

@@ -0,0 +1 @@
+VEC_SEG_STORE(XPR, store_uint16, 2);

hwacha/insns/vssegstb.h

@@ -0,0 +1 @@
+VEC_SEG_ST_STORE(XPR, store_uint8, XS2, 1);

hwacha/insns/vssegstd.h

@@ -0,0 +1 @@
+VEC_SEG_ST_STORE(XPR, store_uint64, XS2, 8);

hwacha/insns/vssegsth.h

@@ -0,0 +1 @@
+VEC_SEG_ST_STORE(XPR, store_uint16, XS2, 2);

hwacha/insns/vssegstw.h

@@ -0,0 +1 @@
+VEC_SEG_ST_STORE(XPR, store_uint32, XS2, 4);

hwacha/insns/vssegw.h

@@ -0,0 +1 @@
+VEC_SEG_STORE(XPR, store_uint32, 4);

hwacha/insns/vsstb.h

@@ -1,2 +0,0 @@
-require_vector;
-VEC_STORE(RD, store_uint8, RS2);

hwacha/insns/vsstd.h

@@ -1,3 +0,0 @@
-require_vector;
-require_xpr64;
-VEC_STORE(RD, store_uint64, RS2);

hwacha/insns/vssth.h

@@ -1,2 +0,0 @@
-require_vector;
-VEC_STORE(RD, store_uint16, RS2);

hwacha/insns/vsstw.h

@@ -1,2 +0,0 @@
-require_vector;
-VEC_STORE(RD, store_uint32, RS2);

hwacha/insns/vsw.h

@@ -1,2 +0,0 @@
-require_vector;
-VEC_STORE(RD, store_uint32, 4);

hwacha/insns/vtcfg.h

@@ -1,5 +0,0 @@
-require_vector;
-nxpr_use = RS1 & 0x3f;
-nfpr_use = RS2 & 0x3f;
-vcfg();
-setvl(0);

hwacha/insns/vvcfg.h

@@ -1,5 +0,0 @@
-require_vector;
-nxpr_use = RS1 & 0x3f;
-nfpr_use = RS2 & 0x3f;
-vcfg();
-setvl(0);

hwacha/insns/vvcfgivl.h

@@ -1,6 +0,0 @@
-require_vector;
-nxpr_use = SIMM & 0x3f;
-nfpr_use = (SIMM >> 6) & 0x3f;
-vcfg();
-setvl(RS1);
-RD = VL;