diff --git a/riscv/csrs.cc b/riscv/csrs.cc
index fbd914fe..3d5a10aa 100644
--- a/riscv/csrs.cc
+++ b/riscv/csrs.cc
@@ -778,6 +778,7 @@ bool misa_csr_t::unlogged_write(const reg_t val) noexcept {
   }
 
   proc->get_mmu()->flush_tlb();
+  proc->build_opcode_map();
 
   return basic_csr_t::unlogged_write(new_misa);
 }
diff --git a/riscv/processor.cc b/riscv/processor.cc
index ffdaa190..11a4d6cc 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -146,6 +146,7 @@ void processor_t::enable_log_commits()
 {
   log_commits_enabled = true;
   mmu->flush_tlb(); // the TLB caches this setting
+  build_opcode_map();
 }
 
 void processor_t::reset()
diff --git a/riscv/processor.h b/riscv/processor.h
index 38781b8b..4939ef55 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -347,6 +347,7 @@ public:
     register_insn(insn, true /* is_custom */);
   }
   void register_extension(extension_t*);
+  void build_opcode_map();
 
   // MMIO slave interface
   bool load(reg_t addr, size_t len, uint8_t* bytes) override;
@@ -429,7 +430,6 @@ private:
   friend class extension_t;
 
   void parse_priv_string(const char*);
-  void build_opcode_map();
   void register_base_instructions();
   insn_func_t decode_insn(insn_t insn);