From 2e873ce98e7afc0304cffe8f6ea2d7afea8efc2a Mon Sep 17 00:00:00 2001 From: Scott Johnson Date: Wed, 6 Oct 2021 09:25:17 -0700 Subject: [PATCH] Don't write vxsat unless it's actually being set to 1 As requested by @marcfedorow: https://github.com/riscv-software-src/riscv-isa-sim/issues/823#issuecomment-936509476 If mstatus.VS exists (i.e. Vector extension is enabled), it will no longer be set to Dirty unless the instruction actually sets vxsat. The mstatus.VS change only affects instructions in the P extension, since Vector instructions will write other vector state and therefore still set mstatus.VS=Dirty. This also affects the commit log. Instructions that don't saturate will no longer show a write to vxsat. --- riscv/decode.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv/decode.h b/riscv/decode.h index 7028c855..3c192a5b 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -2343,7 +2343,7 @@ reg_t index[P.VU.vlmax]; \ } #define P_SET_OV(ov) \ - P.VU.vxsat->write(P.VU.vxsat->read() | ov); + if (ov) P.VU.vxsat->write(1); #define P_SAT(R, BIT) \ if (R > INT##BIT##_MAX) { \