Merge pull request #2049 from riscv-software-src/vector-cleanup

Minor vector-unit cleanup

riscv/vector_unit.cc

@@ -76,7 +76,6 @@ reg_t vectorUnit_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t new
   }
 
   vstart->write_raw(0);
-  setvl_count++;
   return vl->read();
 }
 
@@ -91,7 +90,6 @@ template<class T> T& vectorUnit_t::elt(reg_t vReg, reg_t n, bool UNUSED is_write
   // bits when changing SEW, thus we need to index from the end on BE.
   n ^= elts_per_reg - 1;
 #endif
-  reg_referenced[vReg] = 1;
 
   if (unlikely(p->get_log_commits_enabled() && is_write))
     p->get_state()->log_reg_write[((vReg) << 4) | 2] = {0, 0};
@@ -140,8 +138,6 @@ vectorUnit_t::elt_group(reg_t vReg, reg_t n, bool UNUSED is_write) {
 
   // Element groups per register groups
   for (reg_t vidx = reg_first; vidx <= reg_last; ++vidx) {
-      reg_referenced[vidx] = 1;
-
       if (unlikely(p->get_log_commits_enabled() && is_write)) {
           p->get_state()->log_reg_write[(vidx << 4) | 2] = {0, 0};
       }

riscv/vector_unit.h

@@ -87,21 +87,20 @@ using EGU8x16_t = std::array<uint8_t, 16>;
 class vectorUnit_t
 {
 public:
-  processor_t* p;
-  void *reg_file;
-  char reg_referenced[NVPR];
-  int setvl_count;
-  reg_t vlmax;
-  reg_t vlenb;
-  csr_t_p vxsat;
-  vector_csr_t_p vxrm, vstart, vl, vtype;
-  reg_t vma, vta;
-  reg_t vsew;
-  float vflmul;
-  reg_t altfmt;
-  reg_t ELEN, VLEN;
-  bool vill;
-  bool vstart_alu;
+  processor_t* p = nullptr;
+  void *reg_file = nullptr;
+  int setvl_count = 0;
+  reg_t vlmax = 0;
+  reg_t vlenb = 0;
+  csr_t_p vxsat = 0;
+  vector_csr_t_p vxrm = 0, vstart = 0, vl = 0, vtype = 0;
+  reg_t vma = 0, vta = 0;
+  reg_t vsew = 0;
+  float vflmul = 0;
+  reg_t altfmt = 0;
+  reg_t ELEN = 0, VLEN = 0;
+  bool vill = false;
+  bool vstart_alu = false;
 
   // vector element for various SEW
   template<class T> T& elt(reg_t vReg, reg_t n, bool is_write = false);
@@ -124,28 +123,7 @@ public:
 
   void reset();
 
-  vectorUnit_t():
-    p(0),
-    reg_file(0),
-    reg_referenced{0},
-    setvl_count(0),
-    vlmax(0),
-    vlenb(0),
-    vxsat(0),
-    vxrm(0),
-    vstart(0),
-    vl(0),
-    vtype(0),
-    vma(0),
-    vta(0),
-    vsew(0),
-    vflmul(0),
-    altfmt(0),
-    ELEN(0),
-    VLEN(0),
-    vill(false),
-    vstart_alu(false) {
-  }
+  vectorUnit_t() {}
 
   ~vectorUnit_t() {
     free(reg_file);