From 2aed3d24d987cbb7f63cc0e467814c8884bbf80f Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Fri, 18 Dec 2020 14:16:22 +0530 Subject: [PATCH] Fix processor_t:take_interrupt() for HS-mode interrupts When deciding HS-mode interrupts in processor_t:take_interrupt() we should use "~state.hideleg" instead of "~MIP_VS_MASK" because VS interrupt bits are writeable in HIDELEG CSR. Signed-off-by: Anup Patel --- riscv/processor.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index 76a54172..24131140 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -539,7 +539,7 @@ void processor_t::take_interrupt(reg_t pending_interrupts) enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled; if (enabled_interrupts == 0) { // HS-ints have higher priority over VS-ints - deleg = state.mideleg & ~MIP_VS_MASK; + deleg = state.mideleg & ~state.hideleg; status = (state.v) ? state.vsstatus : state.mstatus; hsie = get_field(status, MSTATUS_SIE); hs_enabled = state.prv < PRV_S || (state.prv == PRV_S && hsie);