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add BSD license

confprec
Andrew Waterman 13 years ago
parent
commit
28ac3dbd81
  1. 24
      LICENSE
  2. 2
      riscv/cachesim.cc
  3. 2
      riscv/cachesim.h
  4. 2
      riscv/common.h
  5. 2
      riscv/decode.h
  6. 2
      riscv/disasm.cc
  7. 2
      riscv/disasm.h
  8. 2
      riscv/htif.cc
  9. 2
      riscv/htif.h
  10. 2
      riscv/insn_header.h
  11. 2
      riscv/interactive.cc
  12. 2
      riscv/memtracer.h
  13. 2
      riscv/mmu.cc
  14. 2
      riscv/mmu.h
  15. 2
      riscv/opcodes.h
  16. 2
      riscv/pcr.h
  17. 2
      riscv/processor.cc
  18. 2
      riscv/processor.h
  19. 2
      riscv/riscv-isa-run.cc
  20. 2
      riscv/sim.cc
  21. 2
      riscv/sim.h
  22. 2
      riscv/trap.cc
  23. 2
      riscv/trap.h

24
LICENSE

@ -0,0 +1,24 @@
Copyright (c) 2013, The Regents of the University of California (Regents).
All Rights Reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the Regents nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.

2
riscv/cachesim.cc

@ -1,3 +1,5 @@
// See LICENSE for license details.
#include "cachesim.h"
#include "common.h"
#include <cstdlib>

2
riscv/cachesim.h

@ -1,3 +1,5 @@
// See LICENSE for license details.
#ifndef _RISCV_CACHE_SIM_H
#define _RISCV_CACHE_SIM_H

2
riscv/common.h

@ -1,3 +1,5 @@
// See LICENSE for license details.
#ifndef _RISCV_COMMON_H
#define _RISCV_COMMON_H

2
riscv/decode.h

@ -1,3 +1,5 @@
// See LICENSE for license details.
#ifndef _RISCV_DECODE_H
#define _RISCV_DECODE_H

2
riscv/disasm.cc

@ -1,3 +1,5 @@
// See LICENSE for license details.
#include "disasm.h"
#include <string>
#include <vector>

2
riscv/disasm.h

@ -1,3 +1,5 @@
// See LICENSE for license details.
#ifndef _RISCV_DISASM_H
#define _RISCV_DISASM_H

2
riscv/htif.cc

@ -1,3 +1,5 @@
// See LICENSE for license details.
#include "htif.h"
#include "sim.h"
#include <unistd.h>

2
riscv/htif.h

@ -1,3 +1,5 @@
// See LICENSE for license details.
#ifndef _HTIF_H
#define _HTIF_H

2
riscv/insn_header.h

@ -1,3 +1,5 @@
// See LICENSE for license details.
#include "processor.h"
#include "config.h"
#include "sim.h"

2
riscv/interactive.cc

@ -1,3 +1,5 @@
// See LICENSE for license details.
#include "sim.h"
#include "htif.h"
#include <sys/mman.h>

2
riscv/memtracer.h

@ -1,3 +1,5 @@
// See LICENSE for license details.
#ifndef _MEMTRACER_H
#define _MEMTRACER_H

2
riscv/mmu.cc

@ -1,3 +1,5 @@
// See LICENSE for license details.
#include "mmu.h"
#include "sim.h"
#include "processor.h"

2
riscv/mmu.h

@ -1,3 +1,5 @@
// See LICENSE for license details.
#ifndef _RISCV_MMU_H
#define _RISCV_MMU_H

2
riscv/opcodes.h

@ -1,3 +1,5 @@
// See LICENSE for license details.
DECLARE_INSN(movn, 0x6f7, 0x1ffff)
DECLARE_INSN(vfsstw, 0x150f, 0x1ffff)
DECLARE_INSN(remuw, 0x7bb, 0x1ffff)

2
riscv/pcr.h

@ -1,3 +1,5 @@
// See LICENSE for license details.
#ifndef _RISCV_PCR_H
#define _RISCV_PCR_H

2
riscv/processor.cc

@ -1,3 +1,5 @@
// See LICENSE for license details.
#include "processor.h"
#include "common.h"
#include "config.h"

2
riscv/processor.h

@ -1,3 +1,5 @@
// See LICENSE for license details.
#ifndef _RISCV_PROCESSOR_H
#define _RISCV_PROCESSOR_H

2
riscv/riscv-isa-run.cc

@ -1,3 +1,5 @@
// See LICENSE for license details.
#include "sim.h"
#include "htif.h"
#include "cachesim.h"

2
riscv/sim.cc

@ -1,3 +1,5 @@
// See LICENSE for license details.
#include "sim.h"
#include "htif.h"
#include <sys/mman.h>

2
riscv/sim.h

@ -1,3 +1,5 @@
// See LICENSE for license details.
#ifndef _RISCV_SIM_H
#define _RISCV_SIM_H

2
riscv/trap.cc

@ -1,3 +1,5 @@
// See LICENSE for license details.
#include "trap.h"
const char* trap_name(trap_t t)

2
riscv/trap.h

@ -1,3 +1,5 @@
// See LICENSE for license details.
#ifndef _RISCV_TRAP_H
#define _RISCV_TRAP_H

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