riscv
/
riscv-isa-sim
mirror of https://github.com/riscv-software-src/riscv-isa-sim.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
Browse Source

doc: update readme for vector 0.9 

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
pull/475/head
Chih-Min Chao 6 years ago
parent
5ea3ef76d2
commit
2469a57166
1 changed files with 1 additions and 1 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 2
      README.md

2
README.md
View File

@ -18,7 +18,7 @@ Spike supports the following RISC-V ISA features:
- D extension, v2.2
- Q extension, v2.2
- C extension, v2.0
- V extension, v0.9-draft-20200403, w/ Zvlsseg, w/o Zvamo/Zvediv, (_requires a 64-bit host_)
- V extension, v0.9, w/ Zvlsseg/Zvamo/Zvqmac, w/o Zvediv, (_requires a 64-bit host_)
- Conformance to both RVWMO and RVTSO (Spike is sequentially consistent)
- Machine, Supervisor, and User modes, v1.11
- Debug v0.14

Write Preview
Loading…
Cancel
Save